TI SN65DSI83TPAPRQ1

Compliant with automotive application requirements, implementing MIPI D-PHY version 1.00.00 physical layer frontend and version 1.02.00 Display Serial Interface (DSI). The single-port DSI receiver supports configurable 1, 2, 3, or 4 D-PHY data lanes per port, with each lane operating at up to 1Gbps. Supports 18bpp and 24bpp DSI video streams in RGB666 and RGB888 formats, with maximum resolution up to 60fps WUXGA 1920×1200 (18bpp and 24bpp color, using reduced blanking), suitable for 60fps 1366×768/1280×800 (18bpp and 24bpp). For single-link LVDS output, supports single-port DSI to single-link LVDS operating mode, with LVDS output clock range of 25MHz to 154MHz. The LVDS pixel clock can use either a free-running continuous D-PHY clock or an external reference clock (REFCLK), with 1.8V main VCC supply. The bridge decodes MIPI DSI 18bpp RGB666 and 24bpp RGB888 video streams and converts the formatted video data stream to LVDS output (pixel clock range: 25MHz to 154MHz), providing single-link LVDS (4 data lanes per link), with partial line buffering implemented to accommodate data flow mismatch between the DSI and LVDS interfaces.

• AEC-Q100 compliant
• Device temperature grade 2: ambient operating temperature range -40°C to +105°C
• Device HBM ESD classification level 3A
• Device CDM ESD classification level C6
• Implements MIPI D-PHY version 1.00.00 physical layer front-end and display serial interface (DSI) version 1.02.00
• Single-channel DSI receiver configurable with 1, 2, 3, or 4 D-PHY data lanes per channel, operating at up to 1Gbps per lane
• Supports 18bpp and 24bpp DSI video streams in RGB666 and RGB888 formats
• Maximum resolution up to 60fps WUXGA 1920×1200 (18bpp and 24bpp color with reduced blanking), suitable for 60fps 1366×768/1280×800 (18bpp and 24bpp)
• Single-link LVDS output supporting single-channel DSI to single-link LVDS operating mode
• LVDS output clock range: 25MHz to 154MHz
• LVDS pixel clock supports free-running continuous D-PHY clock or external reference clock (REFCLK)
• 1.8V main VCC supply
• Low-power features including shutdown mode, low LVDS output voltage swing, common mode, and MIPI ultra-low power state (ULPS) support
• LVDS channel swap (SWAP) and LVDS pin order reversal for simplified PCB routing
• 64-pin 10mm×10mm HTQFP (PAP) PowerPAD IC package

• Infotainment head units with integrated displays
• Infotainment head units with remote displays
• Rear-seat entertainment systems
• Hybrid vehicle instrument clusters
• Portable navigation devices
• Industrial HMI and displays