SILICON LABS SI5317C-C-GMR

The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications that require jitter attenuation without clock multiplication. The Si5317 accepts a single clock input ranging from 1 to 711 MHz and generates two low jitter clock outputs at the same frequency. The clock frequency range and loop bandwidth are selectable from a simple look-up table. The Si5317 provides jitter attenuation on any frequency in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user selectable, providing jitter performance optimization at the application level.

• Provides jitter attenuation for any clock frequency
• One clock input / two clock outputs
• Input/output frequency range: 1–711 MHz
• Ultra low jitter: 300 fs (12 kHz–20 MHz) typical
• Simple pin control interface
• Selectable loop bandwidth for jitter attenuation: 60 Hz - 8.4 kHz
• Meets OC-192 GR-253-CORE jitter specifications
• Selectable output clock signal format: LVPECL, LVDS, CML or CMOS
• Single supply: 1.8, 2.5, or 3.3 V
• Loss of lock and loss of signal alarms
• VCO freeze during LOS/LOL
• On-chip voltage regulator with high PSRR
• Small size: 6×6 mm, 36-QFN
• Wide temperature range: -40 to +85 °C

• Data converter clocking
• Wireless infrastructure
• Networking, SONET/SDH
• Switches and routers
• Medical instrumentation
• Test and measurement