TI LMK05318RGZT

The LMK05318 is a high-performance network synchronizer clock device that offers jitter attenuation, clock generation, advanced clock monitoring, and excellent hitless switching performance to meet the strict timing requirements of communication infrastructure and industrial applications. This device features ultra-low jitter and high power supply noise rejection (PSNR) performance, which can reduce the bit error rate (BER) in high-speed serial links. It can use TI's proprietary bulk acoustic wave (BAW) VCO technology to generate output clocks with 50 fs RMS jitter, independent of the jitter and frequency of the XO and reference inputs. The DPLL supports a programmable loop bandwidth for jitter and drift attenuation, while the two APLLs support fractional frequency conversion, enabling flexible clock generation. The synchronization options supported on the DPLL include hitless switching with phase removal, digital holdover, and a DCO mode with a frequency step of less than 0.001 ppb (parts per billion), enabling precise clock control (IEEE 1588 PTP slave operation). The DPLL can phase-lock to a 1 PPS (pulses per second) reference input and supports an optional zero-delay mode on one output for deterministic input-to-output phase calibration with a programmable offset voltage. The advanced reference input monitoring block ensures robust clock fault detection and helps minimize output clock disturbances in the event of a loss of reference (LOR). The device can use a common low-frequency TCXO or OCXO to set the free-running or holdover output frequency stability according to synchronization standards. Otherwise, when free-running or holdover frequency stability and drift are not critical, the device can use a standard XO. The device can be fully programmed via the I²C or SPI interface and supports custom frequency configuration via an internal EEPROM or ROM after power-up. The EEPROM is pre-programmed at the factory and can be programmed in-system as needed.

• One DPLL featuring:
• Hitless switching: ±50ps phase transient
• Programmable loop bandwidth with fast lock
• Standards-compliant synchronization and holdover using low-cost TCXO/OCXO
• Two APLLs with industry-leading performance:
• 50fs RMS jitter at 312.5MHz (APLL1)
• 125fs RMS jitter at 155.52MHz (APLL2)
• Two reference clock inputs with priority-based input selection and digital holdover on reference loss
• Eight clock outputs with programmable drivers
• Up to 6 distinct output frequencies
• AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8V LVCMOS output formats
• EEPROM/ROM for custom clock configuration at power-up
• Flexible configuration options
• Input and output: 1Hz (1PPS) to 800MHz
• XO/TCXO/OCXO input: 10 to 100MHz
• DCO mode: < 0.001ppb/step for precise clock control (IEEE 1588 PTP slave operation)
• Advanced clock monitoring and status
• I²C or SPI interface
• PSNR: –83dBc (50mVₚ₋ₚ noise on 3.3V supply)
• 3.3V supply with 1.8V, 2.5V, or 3.3V outputs
• Industrial temperature range: -40°C to +85°C

• SyncE (G.8262), SONET/SDH (Stratum 3/3E, G.813, GR-1244, GR-253), IEEE 1588 PTP slave clock, or optical transport network (G.709)
• 400G line cards and network cards for Ethernet switches and routers
• Wireless base stations (BTS), wireless backhaul
• Test & measurement, medical imaging
• Jitter attenuation, wander filtering, and reference clock generation for 56G/112G PAM-4 PHY, ASIC, FPGA, SoC, and processors