MICROCHIP 23LC1024T-I/ST

The 23A1024/23LC1024 are 1 Mbit Serial SRAM devices. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK), a data in line (Sl) and a data out line (SO). Access to the device is controlled through a Chip Select (CS) input. Additionally, SDI (Serial Dual Interface) and SQl (Serial Quad Interface) is supported if your application needs faster data rates. This device also supports unlimited reads and writes to the memory array. The 23A1024/23LC1024 is available in standard packages including 8-lead SOIC, PDIP and advanced 8-lead TSSOP. The 23A1024/23LC1024 is an 1 Mbit Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPl) port of many of today's popular microcontroller families. It may also interface with microcontrollers that do not have a built-in SPl port by using discrete I/O lines programmed properly in firmware to match the SPl protocol. In addition, the 23A1024/23LC1024 is capable of operation in SDl and SQI modes. In SDl mode, the SI and SO data lines are bidirectional, allowing the transfer of two bits per clock pulse. In SQl mode, two additional data lines enable the transfer of four bits per clock pulse. The 23A1024/23LC1024 contains an 8-bit instruction register. The device is accessed via the Sl pin, with data being clocked in on the rising edge of SCK. The CS pin must be low for the entire operation. The 23X1024 has three modes of operation that are selected by setting bits 7 and 6 in the MODE register. The modes of operation are Byte, Page and Burst. Byte Operation - is selected when bits 7 and 6 in the MODE register are set to 00. In this mode, the read/write operations are limited to only one byte. The Command followed by the 24-bit address is clocked into the device and the data to/from the device is transferred on the next eight clocks. Page Operation - is selected when bits 7 and 6 in the MODE register are set to 10. The 23X1024 has 4096 pages of 32 bytes. In this mode, the read and write operations are limited to within the addressed page (the address is automatically incremented internally). If the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page. Sequential Operation - is selected when bits 7 and 6 in the MODE register are set to 01. Sequential operation allows the entire array to be written to and read from. The internal address counter is automatically incremented and page boundaries are ignored. When the internal address counter reaches the end of the array, the address counter will roll over to 0x00000. The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 23A1024/23LC1024 followed by the 24-bit address, with the first seven MSB's of the address being “don't care" bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. If operating in Sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFFh), the address counter rolls over to address 00000h, allowing the read cycle to be continued.

• SPI Bus Interface: - SPI compatible - SDl (dual) and SQl (quad) compatible - 20 MHz Clock rate for all modes
• Low-Power CMOS Technology: - Read Current: 3 mA at 5.5V, 20 MHz - Standby Current: 4 μA at +85℃
• Unlimited Read and Write Cycles
• Zero Write Time
• 128Kx8 -bit Organization: - 32-byte page
• Byte, Page and Sequential Mode for Reads and Writes
• High Reliability
• Temperature Ranges Supported: - Industrial (I): -40℃ to +85℃ - Automotive (E): -40℃ to +125℃
• RoHS Compliant
• 8 Lead SOIC, TSSOP and PDIP Packages