The ST16C550 (550) is a universal asynchronous receiver and transmitter with 16 byte transmit and receive FIFO. It operates at 2.97 to 5.5 volts. A programmable baud rate generator can select transmit and receive clock rates from 50 bps to 1.5 Mbps.
The ST16C550 is an improved version of the NS16C550 UART with higher operating speed and lower access time. The ST16C550 on board status registers provides the error conditions, type and status of the transfer operation being performed. Included is complete MODEM control capability, and a processor interrupt system that may be software tailored to the user’s requirements. The ST16C550 provides internal loopback capability for on board diagnostic testing.
The ST16C550 is available in 40 pin PDIP, 44 pin PLCC, and 48 pin TQFP packages. It is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements.
The ST16C550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The ST16C550 represents such an integration with greatly enhanced features. The ST16C550 is fabricated with an advanced CMOS process.
The ST16C550 is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of 1 byte provided in the 16C450. The ST16C550 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the ST16C550 by the larger transmit and receive FIFO’s. This allows the external processor to handle more networking tasks within a given time. The 4 selectable levels of FIFO trigger provided for maximum data throughput performance especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption.
The ST16C550 is capable of operation to 1.5Mbps with a 24 MHz crystal or external clock input. With a crystal of 14.7464 MHz and through a software option, the user can select data rates up to 460.8Kbps or 921.6Kbps.
MaxLinear ST16C550CJ44TR-F