TI CD4516BPWR

CD4510B Presettable BCD Up/Down Counter and the CD4516 Presettable Binary Up/Down Counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the.RESET line, and can be preset to any binary number present on the jam inputs by a high.level on the PRESET ENABLE line. The CD45108 will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode. If the CARRY-IN input is held low, the counter. advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage. The CD4510B and CD4516B can be cascaded in the ripple mode by connecting the CARRY. OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOwN input must change while the clock is high. This method provides a clean clock signal to the subse. quent counting stage. These devices are similar to types MC14510 and MC14516. The CD4510B and CD4516B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD4516B types also are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix).

• Medium-speed operation -- f_CL = 8 MHz typ. at 10 V
• Synchronous internal carry propagation
• Reset and Preset capability
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized symmetrical output characteristics
• Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25℃
• Noise margin (full package-temperature range): 1 V at V_DD = 5 V, 2 V at V_DD = 10 V, 2.5 V at V_DD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of Φ'z' Series CMOS Devices"

• Up/Down difference counting
• Multistage synchronous counting
• Multistage ripple counting
• Synchronous frequency dividers