TI SN74LVC2G80DCUR

This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation. When data at the data (D) input meets the setup time requirement, the data is transferred to the overline{Q} output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff . The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Available in the NanoFree™ Package
• Supports 5-V Vcc Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.2 ns at 3.3 V
• Low Power Consumption, 10 μA Max ICC
• Typical VoLP (Output Ground Bounce) < 0.8 V at VCC = 3.3V, TA = 25℃
• Typical V0HV (Output VoH Undershoot) > 2 V at VCC = 3.3V, TA = 25℃
• Ioff Feature Supports Live Insertion, Partial Power-Down and Back Drive Protection Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)