TI SN74LVC2G74MDCUTEP

This single positive edge triggered D-type flip-flop is designed for 1.65-V to 5.5 V CC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Controlled Baseline
• One Assembly Site One Test Site One Fabrication Site
• Extended Temperature Performance of -55℃ to 125℃
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree
• Supports 5-V Vcc Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 7.9 ns at 3.3 V
• Low Power Consumption, 10 μA Max ICC
• ±24 mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3V, TA = 25℃
• Typical VOHV (Output vOH Undershoot) > 2 V at VCC = 3.3V, TA = 25℃
• Ioff Supports Partial Power Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)