TI VSP5610RSHR

VSP5610/11/12 are high-speed, high-performance 16-bit ADCs with four independent sampling circuit channels for multi-output CCD and CMOS image sensors. Pixel data from the sensor is sampled by SH or CDS circuits, then converted to digital data by the ADC. Data output is selectable between LVDS and CMOS modes.

Analog gain: 0.5V/V to 3.5V/V in 3/64-V/V steps Digital gain: 1V/V to 2V/V in 1/256-V/V steps

The VSP5610/11/12 includes a programmable gain to support pixel-level reflectance caused by luminance variations. An integrated DAC is available for adjusting the offset level of analog input signals. Additionally, a TG and several devices for controlling sensor operation are integrated.

The VSP5610/11/12 operates at 1.65V to 1.95V for core voltage and 3.0V to 3.6V for I/O. The core voltage is supplied by a built-in LDO.

Timing generator: Fast transfer clock: eight signals Slow transfer clock: six signals

Timing adjustment resolution: tMCLK/48

• Input clamp/input reference level: internal/external (selectable)
• Reference DAC: 0.5V, 1.1V, 1.5V, 2V
• SPI: 3-wire serial GPIO: four ports

• Quad-channel CCD/CMOS signal: 2-channel, 4-channel, or 4-channel (optional)
• Power supply: 3.3V only (typical) (built-in LDO, 3.3V to 1.8V)
• Maximum conversion rate:
  • VSP5610: 35 MSPS
  • VSP5611: 50 MSPS
  • VSP5612: 70 MSPS

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