Zilog Z84C4210PEG

The Z80 SIO (here in after referred to as the Z80 SIO or, SIO). Serial Input/Output Controller is a dual-channel data communication interface with outstanding versatility and capability. Its basic function is a serial-to-parallel, parallel-to-serial converter/controller that can be programmed by a CPU for a broad range of serial communication applications. The device supports all popular asynchronous and synchronous protocols, byte or bit oriented, and performs all of the functions traditionally performed by UARTs, USARTs, and synchronous communication controllers combined, plus additional functions typically performed by the CPU. Moreover it has two fully-independent channels, with an exceptionally sophisticated interrupt structure that allows very fast transfers. Full intertacing is provided for CPU or DMA control. In addition to data communication, the circuit can handle virtually all types of serial I/O with fast, or slow, peripheral devices. While designed primarily as a member of the Z80 family, its versatility makes it well suited to many other CPUs. The Z80 SIO uses a single +5V power supply and the standard Z80 family single-phase clock. The SIO/0, SIO/1, and SIO/2 are packaged in a 40-pin DIP, the SIO/4 is packaged in a 44-pin PLCC.

• Two independent full-duplex channels, with separate control and status lines for each channel or other devices.
• Data rate in the x1 clock mode from 0 to 2.0M bits/second with a 10 MHz clock.
• NMOS version for high performance solutions, CMOS version for applications requiring low power consumption.
• NMOS Z844x04 - 4 MHz, Z844x06 - 6.17 MHz (Where x is the designator for the bonding option; 0, 1, 2 or 4).
• CMOS Z84C4x06 - 6 MHz, Z84C4x08 - DC to 8 MHz, Z84C4x10 - 10 MHz (Where x is the designator for the bonding option, 0, 1, 2, 3 or 4).
• 16 MHz version supports a 144 MHz CPU clock operation.
• Asynchronous protocols: everything necessary for complete messages in 5, 6, 7, or 8 bits/character. Includes variable stop bits and several clock-rate multipliers, break generation and detection; parity, overrun and framing error detection.
• Synchronous protocols: everything necessary for complete bit- or byte oriented messages in 5, 6, 7, or 8 bits/character, including IBM Bisync, SDLC, HDLC, CCITT-X.25 and others. Automatic CRC generation/checking, sync character and zero insertion/deletion, abort generation/detection, and lag insertion.
• Receiver data registers (quadruple buffered), transmitter registers (triple buffered).
• Highly sophisticated and flexible daisy-chain interrupt vectoring for interrupts without external logic.