Nexperia 74HCT174D,653
| Manufacturer | |
| MPN | 74HCT174D,653 |
| LCSC Part # | C2441404 |
| Packaging | SO-16 |
| Customer # | |
| Key Attributes | 4.5V~5.5V 6 1 35ns@4.5V,50pF SO-16 Flip Flops RoHS |
| Datasheet |  Nexperia 74HCT174D,653 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | Nexperia | |
| Packaging | SO-16 | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 4.5V~5.5V | |
| Number of Bits per Element | 6 | |
| Series | 74HCT Series | |
| Output Type | - | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 4mA | |
| Current - Output Low(IOL) | 5.2mA | |
| Quiescent Current | 8uA | |
| Propagation Delay | 35ns@4.5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features
- Wide supply voltage range from 2.0 to 6.0 V
- CMOS low power dissipation
- High noise immunity
- Input levels: For 74HC174: CMOS level For 74HCT174: TTL level
- Six edge-triggered D-type flip-flops
- Asynchronous master reset
- Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0V to 6.0 V)
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.4495 | $ 0.45 |
| 10+ | $ 0.3554 | $ 3.55 |
| 30+ | $ 0.3148 | $ 9.44 |
| 100+ | $ 0.2645 | $ 26.45 |
| 500+ | $ 0.2418 | $ 120.90 |
| 1,000+ | $ 0.2288 | $ 228.80 |
Standard Packaging2500/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | Nexperia | |
| Packaging | SO-16 | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 4.5V~5.5V | |
| Number of Bits per Element | 6 | |
| Series | 74HCT Series | |
| Output Type | - | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 4mA | |
| Current - Output Low(IOL) | 5.2mA | |
| Quiescent Current | 8uA | |
| Propagation Delay | 35ns@4.5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features
- Wide supply voltage range from 2.0 to 6.0 V
- CMOS low power dissipation
- High noise immunity
- Input levels: For 74HC174: CMOS level For 74HCT174: TTL level
- Six edge-triggered D-type flip-flops
- Asynchronous master reset
- Complies with JEDEC standards JESD8C (2.7 V to 3.6 V) JESD7A (2.0V to 6.0 V)
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |