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EDA ModelsEasyEDA
ST STM32H533VET6
| Manufacturer | |
| MPN | STM32H533VET6 |
| LCSC Part # | C22808547 |
| Packaging | LQFP-100(14x14) |
| Customer # | |
| Key Attributes | ARM Cortex-M33 32 Bit 250MHz 80 LQFP-100(14x14) Microcontrollers RoHS |
| Datasheet |  ST STM32H533VET6 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | ST | |
| Packaging | LQFP-100(14x14) | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.71V~3.6V | |
| EEPROM | - | |
| Program Storage Size | 512KB | |
| CPU Core | ARM Cortex-M33 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 250MHz | |
| Oscillator Type | Built-in+External | |
| Number of I/O | 80 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 540 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Includes ST state-of-the-art patented technology
- Arm Cortex-M33 CPU with TrustZone, FPU, frequency up to 250 MHz, MPU, 375 DMIPS (Dhrystone 2.1)
- 8-Kbyte instruction cache allowing 0-wait-state execution from flash and external memories
- 4-Kbyte data cache for external memories
- 1.5 DMIPS/MHz (Dyrystone 2.1)
- 1023 CoreMark (4.092 CoreMark/MHz)
- Up to 512 Kbytes of embedded flash memory with ECC, two banks read-while-write
- Up to 48-Kbyte per bank with high-cycling capability (100 K cycles) for data flash
- 2-Kbyte OTP (one-time programmable)
- 272 Kbytes of SRAM (80-Kbyte SRAM2 with ECC)
- 2 Kbytes of backup SRAM available in the lowest power modes
- Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, NOR/NAND memories
- One Octo-SPI memory interface with support for serial PSRAM/NAND/MOR, hyper RAM/flash frame formats
- One SD/SDIO/MMC interface
- Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
- External oscillators: 4 - 50 MHz HSE, 32.768 kHz LSE
- Up to 112 fast I/Os with interrupt capability (most of them 5 V-tolerant)
- Up to ten I/Os with independent supply down to 1.08 V
- Sleep, Stop, and Standby modes
- VBAT supply for RTC, 32 backup registers (32-bit)
- Arm TrustZone with Armv8-M mainline security extension
- Up to eight configurable SAU regions
- TrustZone aware and securable peripherals
- Flexible life cycle scheme with secure debug authentication
- SESIP3 and PSA Level 3 certified assurance target
- Preconfigured immutable root of trust (ST-iROT)
- SFI (secure firmware installation)
- Root of trust thanks to unique boot entry and secure hide protection area (HDP)
- Secure data storage with hardware unique key (HUK)
- Secure firmware upgrade support with TF-M
- Two AES coprocessors, including one with DPA resistance
- Public key accelerator, DPA resistant
- On-the-fly decryption of Octo-SPI external memories
- HASH hardware accelerator
- True random number generator, NIST SP800 - 90B compliant
- 96-bit unique ID
- Active tampers
- Two DMA controllers to offload the CPU
- Two dual-port DMAs with FIFO
- 1.71 V to 3.6V application supply and I/O
- POR, PDR, PVD, and BOR
- Embedded regulator with configurable scalable output to supply the digital circuitry
- Up to 16 timers
- Ten 16-bit timers (including two low-power 16-bit timers available in StOp mode)
- Two 32-bit timers with up to four IC/OC/PWM or pulse counters and quadrature (incremental) encoder input
- Two watchdogs
- Two SysTick timers
- Up to 34 communication interfaces
- Up to three I2Cs Fmt (SMBus/PMBus)
- Two I3Cs
- Up to six U(S)ARTs (ISO7816 interface, LIN, IrDA, modem control) and one LPUART
- Up to four SPIs, including three muxed in full-duplex I2S audio class accuracy via internal audio PSL or external clock, and up to four additional SPIs from four USARTs when configured in Synchronous mode (one additional SPI with OctoSPI)
- Two FDCAN controllers
- One 8 - to 14-bit camera interface
- One 16-bit parallel slave synchronous-interface
- One HDMI-CEC
- One USB 2.0 full-speed host and device (crystal-less)
- One USB Type-C/USB Power Delivery r3.1
- Two 12-bit ADCs with up to 5 Msps in 12-bit
- One 12-bit DAC with two channels
- Digital temperature sensor
- Voltage reference buffer
- Authenticated debug and flexible device life cycle
- Serial wire-debug (SWD), JTAG, Embedded Trace Macrocell (ETM)
- ECOPACK2 compliant packages
In-Stock: 5
5 In stock, ships now
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 7.9551 | $ 7.96 |
| 10+ | $ 6.8639 | $ 68.64 |
| 30+ | $ 6.1995 | $ 185.99 |
| 100+ | $ 5.6418 | $ 564.18 |
Standard Packaging540/Full Tray | ||
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | ST | |
| Packaging | LQFP-100(14x14) | |
| Operating Temperature | -40℃~+85℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 1.71V~3.6V | |
| EEPROM | - | |
| Program Storage Size | 512KB | |
| CPU Core | ARM Cortex-M33 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 250MHz | |
| Oscillator Type | Built-in+External | |
| Number of I/O | 80 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 540 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Includes ST state-of-the-art patented technology
- Arm Cortex-M33 CPU with TrustZone, FPU, frequency up to 250 MHz, MPU, 375 DMIPS (Dhrystone 2.1)
- 8-Kbyte instruction cache allowing 0-wait-state execution from flash and external memories
- 4-Kbyte data cache for external memories
- 1.5 DMIPS/MHz (Dyrystone 2.1)
- 1023 CoreMark (4.092 CoreMark/MHz)
- Up to 512 Kbytes of embedded flash memory with ECC, two banks read-while-write
- Up to 48-Kbyte per bank with high-cycling capability (100 K cycles) for data flash
- 2-Kbyte OTP (one-time programmable)
- 272 Kbytes of SRAM (80-Kbyte SRAM2 with ECC)
- 2 Kbytes of backup SRAM available in the lowest power modes
- Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, NOR/NAND memories
- One Octo-SPI memory interface with support for serial PSRAM/NAND/MOR, hyper RAM/flash frame formats
- One SD/SDIO/MMC interface
- Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
- External oscillators: 4 - 50 MHz HSE, 32.768 kHz LSE
- Up to 112 fast I/Os with interrupt capability (most of them 5 V-tolerant)
- Up to ten I/Os with independent supply down to 1.08 V
- Sleep, Stop, and Standby modes
- VBAT supply for RTC, 32 backup registers (32-bit)
- Arm TrustZone with Armv8-M mainline security extension
- Up to eight configurable SAU regions
- TrustZone aware and securable peripherals
- Flexible life cycle scheme with secure debug authentication
- SESIP3 and PSA Level 3 certified assurance target
- Preconfigured immutable root of trust (ST-iROT)
- SFI (secure firmware installation)
- Root of trust thanks to unique boot entry and secure hide protection area (HDP)
- Secure data storage with hardware unique key (HUK)
- Secure firmware upgrade support with TF-M
- Two AES coprocessors, including one with DPA resistance
- Public key accelerator, DPA resistant
- On-the-fly decryption of Octo-SPI external memories
- HASH hardware accelerator
- True random number generator, NIST SP800 - 90B compliant
- 96-bit unique ID
- Active tampers
- Two DMA controllers to offload the CPU
- Two dual-port DMAs with FIFO
- 1.71 V to 3.6V application supply and I/O
- POR, PDR, PVD, and BOR
- Embedded regulator with configurable scalable output to supply the digital circuitry
- Up to 16 timers
- Ten 16-bit timers (including two low-power 16-bit timers available in StOp mode)
- Two 32-bit timers with up to four IC/OC/PWM or pulse counters and quadrature (incremental) encoder input
- Two watchdogs
- Two SysTick timers
- Up to 34 communication interfaces
- Up to three I2Cs Fmt (SMBus/PMBus)
- Two I3Cs
- Up to six U(S)ARTs (ISO7816 interface, LIN, IrDA, modem control) and one LPUART
- Up to four SPIs, including three muxed in full-duplex I2S audio class accuracy via internal audio PSL or external clock, and up to four additional SPIs from four USARTs when configured in Synchronous mode (one additional SPI with OctoSPI)
- Two FDCAN controllers
- One 8 - to 14-bit camera interface
- One 16-bit parallel slave synchronous-interface
- One HDMI-CEC
- One USB 2.0 full-speed host and device (crystal-less)
- One USB Type-C/USB Power Delivery r3.1
- Two 12-bit ADCs with up to 5 Msps in 12-bit
- One 12-bit DAC with two channels
- Digital temperature sensor
- Voltage reference buffer
- Authenticated debug and flexible device life cycle
- Serial wire-debug (SWD), JTAG, Embedded Trace Macrocell (ETM)
- ECOPACK2 compliant packages
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |