JSMSEMI 74HC165D-JSM

The 74HC165D-JSM devices are 8-bit parallelload shiftregisters that, when clocked, shift the data toward aserial (Ωₕ) output. Parallelin access to each stage is provided by eight individual direct data (A - H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The 74HC16 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a lowto-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CL is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.

• Wide Operating Voltage Range of 2 V to 6 V
• Outputs Can Drive Up To 10 LSTTL Loads
• Low Power Consumption, 80 μA Max Icc
• Typical tₚd = 13 ns
• ±4-mA Output Drive at 5 V
• Low Input Current of 1 μA Max
• Complementary Outputs
• Direct Overriding Load (Data) Inputs
• Gated Clock Inputs
• Parallel-to-Serial Data Conversion