TI TMSDVC5402PGE100G4

The TMS320VC5402 fixed-point DSP (hereinafter referred to as the 5402 unless otherwise noted) is based on an advanced modified Harvard architecture with one program memory bus and three data memory buses. The processor features a highly parallel ALU, application-specific hardware logic, on-chip memory, and other on-chip peripherals. The operational flexibility and speed of this DSP are built on a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two reads and one write can be performed in a single cycle. Instructions with parallel store and application-specific instructions can take full advantage of this architecture. Additionally, data can be transferred between data and program spaces. This parallelism supports execution of a powerful set of arithmetic, logic, and bit operations within a single machine cycle. The 5402 also includes control mechanisms for managing interrupts, repeat operations, and function calls.

The TMS320VC5402PGE (144-pin LQFP) package is pin-compatible with the 'LC548, 'LC/VC549, and 'VC5410 devices.

TMS320VC5402 GGU Package (Bottom View)

The following pin assignment table lists each signal quadrant and BGA ball number for the TMS320VC5402GGU (144-pin BGA) package, which is pin-compatible with the 'LC548 and 'LC/VC549 devices.

• Advanced multi-bus architecture with three independent 16-bit data memory buses and one program memory bus
• 40-bit ALU including a 40-bit barrel shifter and two independent 40-bit accumulators
• 17×17-bit parallel multiplier connected to a 40-bit dedicated adder for non-pipelined single-cycle MAC operations
• Compare, Select, and Store Unit (CSSU) for add/compare selection of Viterbi operators
• Exponent encoder for computing the exponent value of a 40-bit accumulator value in a single cycle
• Two address generators with eight auxiliary registers and two Auxiliary Register Arithmetic Units (ARAUs)
• Data bus with bus-hold capability
• Extended addressing mode for 1M×16-bit maximum addressable external program space
• 4K×16-bit on-chip ROM
• 16K×16-bit dual-access on-chip RAM
• Single-instruction repeat and block repeat operations for program code
• Block memory move instructions for efficient program and data management
• Instructions with 32-bit long-word operands
• Instructions with two-operand or three-operand reads
• Arithmetic instructions with parallel store and parallel load
• Conditional store instructions
• Fast interrupt return
• On-chip peripherals
• Software-programmable wait-state generator and programmable memory bank switching
• On-chip PLL clock generator with internal oscillator or external clock source
• Two multichannel buffered serial ports (McBSPs)
• Enhanced 8-bit parallel host port interface (HPI8)
• Two 16-bit timers
• Six-channel DMA controller
• Power control with IDLE1, IDLE2, and IDLE3 instructions and power-down modes
• CLKOUT disable control for turning off CLKOUT
• On-chip scan-based emulation logic, IEEE Std 1149.1 (JTAG) boundary-scan logic
• 10ns (100 MIPS) single-cycle fixed-point instruction execution at 3.3V supply (1.8V core)
• Available in 144-pin plastic low-profile QFP (LQFP) (PGE suffix) and 144-pin BGA (GGU suffix)