RENESAS 72221L15JGI

The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO are high-speed, low-power first-in first-out (FIFO) memories with clocked read/write control. These devices feature 64, 256, 512, 1,024, 2,048, 4,096, and 8,192 x 9-bit memory arrays, respectively. These FIFOs are suited for a wide range of data buffering applications, including graphics processing, LAN, and interprocessor communication. These FIFOs provide 9-bit input and output ports. The input port is controlled by a free-running clock (WCLK) and two write enable pins (WEN1, WEN2). When the write enable pins are asserted, data is written to the synchronous FIFO on each rising clock edge. The output port is controlled by a separate clock pin (RCLK) and two read enable pins (REN1, REN2). The read clock can be tied to the write clock for single-clock operation, or the two clocks can run asynchronously for dual-clock operation. An output enable pin (OE) is provided on the read port for three-state control of the outputs. The synchronous FIFO has two fixed flags: Empty (EF) and Full (FF). Two programmable flags — Almost Empty (PAE) and Almost Full (PAF) — are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. Programmable flag offset loading is controlled by a simple state machine and initiated by asserting the Load pin (LD). These FIFOs are fabricated using high-speed submicron CMOS technology.

• 64 x 9-bit organization (IDT72421)
• 256 x 9-bit organization (IDT72201)
• 512 x 9-bit organization (IDT72211)
• 1,024 x 9-bit organization (IDT72221)
• 2,048 x 9-bit organization (IDT72231)
• 4,096 x 9-bit organization (IDT72241)
• 8,192 x 9-bit organization (IDT72251)
• 10ns read/write cycle time
• Independent read and write clocks
• Dual-port zero fall-through time architecture
• Empty and full flag signals indicate FIFO status
• Programmable almost-empty and almost-full flags settable to any depth
• Programmable almost-empty and almost-full flags default to empty+7 and full-7 respectively
• Output enable places output data bus in high-impedance state
• Advanced submicron CMOS technology
• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin thin quad flat pack (TQFP)
• Industrial temperature range -40°C to +85°C available
• Green parts available

• Graphics
• LAN
• Inter-processor communication