ST M95320-DRDW8TP/K
| Manufacturer | |
| MPN | M95320-DRDW8TP/K |
| LCSC Part # | C2061659 |
| Packaging | TSSOP-8 |
| Customer # | |
| Key Attributes | 32-Kbit serial SPI bus EEPROM - 105 ℃ Operation |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | ST | |
| Packaging | TSSOP-8 | |
| Memory Size | 32Kbit | |
| Voltage - Supply | 1.7V~5.5V | |
| Operating temperature | -40℃~+105℃ | |
| Clock Frequency | 20MHz | |
| Features | Hardware write protection function;Built-in power-on reset (POR);Built-in error correction code (ECC) function;Built-in write enable latch (WEL);Page write protection function | |
| Data Retention - TDR (Year) | 50 Years | |
| Write Cycle Time(tWC) | 4ms | |
| Write Cycle Endurance | 4,000,000 Cycles | |
| Interface | SPI |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 4000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The M95320-DRE is a 32-Kbit serial EEPROM device operating up to 105 ℃. The M95320-DRE is compliant with the level of reliability defined by the AEC-Q100 grade 2. The device is accessed by a simple serial SPl compatible interface running up to 20 MHz. The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95320-DRE is a byte-alterable memory (4096x8 bits) organized as 128 pages of 32 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M95320-DRE offers an additional Identification Page (32 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application para
Features
- Compatible with the Serial Peripheral Interface (SPI) bus
- Memory array - 32 Kbit (4 Kbytes) of EEPROM - Page size: 32 bytes - Write protection by block: 1/4, 1/2 or whole memory - Additional Write lockable Page (ldentification page)
- Extended temperature and voltage range - Up to 105 ℃ (VCC from 1.7 to 5.5 V)
- High speed clock frequency - 20 MHz for VCC ≥ 4.5 V, 10 MHz for VCC ≥ 2.5 V, 5 MHz for VCC ≥ 1.7 V
- Schmitt trigger inputs for noise filtering
- Short Write cycle time - Byte Write within 4 ms - Page Write within 4 ms
- Write cycle endurance - 4 million Write cycles at 25 ℃, 1.2 million Write cycles at 85 ℃, 900 k Write cycles at 105 ℃
- Data retention - more than 50 years at 105 ℃, 200 years at 55 ℃
- ESD Protection (Human Body Model) - 4000V
- Packages RoHS-compliant and halogen-free (ECOPACK2)
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 1.141 | $ 1.14 |
| 10+ | $ 0.944 | $ 9.44 |
| 30+ | $ 0.8366 | $ 25.10 |
| 100+ | $ 0.7145 | $ 71.45 |
| 500+ | $ 0.6608 | $ 330.40 |
| 1,000+ | $ 0.6364 | $ 636.40 |
Standard Packaging4000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | ST | |
| Packaging | TSSOP-8 | |
| Memory Size | 32Kbit | |
| Voltage - Supply | 1.7V~5.5V | |
| Operating temperature | -40℃~+105℃ | |
| Clock Frequency | 20MHz | |
| Features | Hardware write protection function;Built-in power-on reset (POR);Built-in error correction code (ECC) function;Built-in write enable latch (WEL);Page write protection function | |
| Data Retention - TDR (Year) | 50 Years | |
| Write Cycle Time(tWC) | 4ms | |
| Write Cycle Endurance | 4,000,000 Cycles | |
| Interface | SPI |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 4000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The M95320-DRE is a 32-Kbit serial EEPROM device operating up to 105 ℃. The M95320-DRE is compliant with the level of reliability defined by the AEC-Q100 grade 2. The device is accessed by a simple serial SPl compatible interface running up to 20 MHz. The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95320-DRE is a byte-alterable memory (4096x8 bits) organized as 128 pages of 32 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M95320-DRE offers an additional Identification Page (32 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application para
Features
- Compatible with the Serial Peripheral Interface (SPI) bus
- Memory array - 32 Kbit (4 Kbytes) of EEPROM - Page size: 32 bytes - Write protection by block: 1/4, 1/2 or whole memory - Additional Write lockable Page (ldentification page)
- Extended temperature and voltage range - Up to 105 ℃ (VCC from 1.7 to 5.5 V)
- High speed clock frequency - 20 MHz for VCC ≥ 4.5 V, 10 MHz for VCC ≥ 2.5 V, 5 MHz for VCC ≥ 1.7 V
- Schmitt trigger inputs for noise filtering
- Short Write cycle time - Byte Write within 4 ms - Page Write within 4 ms
- Write cycle endurance - 4 million Write cycles at 25 ℃, 1.2 million Write cycles at 85 ℃, 900 k Write cycles at 105 ℃
- Data retention - more than 50 years at 105 ℃, 200 years at 55 ℃
- ESD Protection (Human Body Model) - 4000V
- Packages RoHS-compliant and halogen-free (ECOPACK2)
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |



