ST M95080-DRMN8TP/K
| Manufacturer | |
| MPN | M95080-DRMN8TP/K |
| LCSC Part # | C2061229 |
| Packaging | SO-8 |
| Customer # | |
| Key Attributes | 8-Kbit serial SPI bus EEPROM - 105 °C Operation |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | ST | |
| Packaging | SO-8 | |
| Memory Size | 8Kbit | |
| Voltage - Supply | 1.7V~5.5V | |
| Operating temperature | -40℃~+105℃ | |
| Clock Frequency | 5MHz~20MHz | |
| Features | Hardware write protection function;Built-in power-on reset (POR);Built-in error correction code (ECC) function;Built-in write enable latch (WEL);Page write protection function | |
| Data Retention - TDR (Year) | 50 Years | |
| Write Cycle Time(tWC) | 4ms | |
| Write Cycle Endurance | 4,000,000 Cycles | |
| Interface | SPI |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The M95080-DRE is a 8-Kbit serial EEPROM device operating up to 105 ℃. It is compliant with the level of reliability defined by the AEC-Q100 grade 2. The device is accessed by a simple serial SPI compatible interface running up to 20 MHz. The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95080-DRE is a byte-alterable memory (1024x8 bits) organized as 32 pages of 32 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M95080-DRE offers an additional Identification Page (32 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters.
Features
- Compatible with the Serial Peripheral Interface (SPI) bus
- Memory array – 8 Kbit (1 Kbyte) of EEPROM – Page size: 32 bytes – Write protection by block: 1/4, 1/2 or whole memory – Additional Write lockable Page (Identification page)
- Extended temperature and voltage range – Up to 105 ℃, VCC from 1.7 V to 5.5 V
- High speed clock frequency – 20 MHz for VCC ≥ 4.5 V – 10 MHz for VCC ≥ 2.5 V – 5 MHz for VCC ≥ 1.7 V
- Schmitt trigger inputs for noise filtering
- Short Write cycle time – Byte Write within 4 ms – Page Write within 4 ms
- Write cycle endurance – 4 million Write cycles at 25 ℃ – 1.2 million Write cycles at 85 ℃ – 900 k Write cycles at 105 ℃
- Data retention – more than 50 years at 105 ℃ – 200 years at 55 ℃
- ESD Protection (Human Body Model) – 4000 V
- Packages – RoHS-compliant and halogen-free
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.6221 | $ 0.62 |
| 10+ | $ 0.5651 | $ 5.65 |
| 30+ | $ 0.5375 | $ 16.13 |
| 100+ | $ 0.5098 | $ 50.98 |
| 500+ | $ 0.4935 | $ 246.75 |
| 1,000+ | $ 0.4853 | $ 485.30 |
Standard Packaging2500/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | ST | |
| Packaging | SO-8 | |
| Memory Size | 8Kbit | |
| Voltage - Supply | 1.7V~5.5V | |
| Operating temperature | -40℃~+105℃ | |
| Clock Frequency | 5MHz~20MHz | |
| Features | Hardware write protection function;Built-in power-on reset (POR);Built-in error correction code (ECC) function;Built-in write enable latch (WEL);Page write protection function | |
| Data Retention - TDR (Year) | 50 Years | |
| Write Cycle Time(tWC) | 4ms | |
| Write Cycle Endurance | 4,000,000 Cycles | |
| Interface | SPI |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The M95080-DRE is a 8-Kbit serial EEPROM device operating up to 105 ℃. It is compliant with the level of reliability defined by the AEC-Q100 grade 2. The device is accessed by a simple serial SPI compatible interface running up to 20 MHz. The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M95080-DRE is a byte-alterable memory (1024x8 bits) organized as 32 pages of 32 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M95080-DRE offers an additional Identification Page (32 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters.
Features
- Compatible with the Serial Peripheral Interface (SPI) bus
- Memory array – 8 Kbit (1 Kbyte) of EEPROM – Page size: 32 bytes – Write protection by block: 1/4, 1/2 or whole memory – Additional Write lockable Page (Identification page)
- Extended temperature and voltage range – Up to 105 ℃, VCC from 1.7 V to 5.5 V
- High speed clock frequency – 20 MHz for VCC ≥ 4.5 V – 10 MHz for VCC ≥ 2.5 V – 5 MHz for VCC ≥ 1.7 V
- Schmitt trigger inputs for noise filtering
- Short Write cycle time – Byte Write within 4 ms – Page Write within 4 ms
- Write cycle endurance – 4 million Write cycles at 25 ℃ – 1.2 million Write cycles at 85 ℃ – 900 k Write cycles at 105 ℃
- Data retention – more than 50 years at 105 ℃ – 200 years at 55 ℃
- ESD Protection (Human Body Model) – 4000 V
- Packages – RoHS-compliant and halogen-free
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |

