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EDA ModelsEasyEDA
MICROCHIP ATSAML10D15A-MUT
| Manufacturer | |
| MPN | ATSAML10D15A-MUT |
| LCSC Part # | C2053076 |
| Packaging | QFN-24-EP(4x4) |
| Customer # | |
| Key Attributes | ARM Cortex-M23 32 Bit 32MHz 17 QFN-24-EP(4x4) Microcontrollers RoHS |
| Datasheet |  MICROCHIP ATSAML10D15A-MUT |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | QFN-24-EP(4x4) | |
| DAC (Bit) | 10bit | |
| ADC (Bit) | 12bit | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 1.62V~3.63V | |
| Program Memory Type | FLASH | |
| EEPROM | 2KB | |
| Program Storage Size | 32KB | |
| CPU Core | ARM Cortex-M23 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 32MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 17 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 6000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Operating Conditions: 1.62V to 3.63V, -40°C to +125°C, DC to 32 MHz
- Core: 32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS) Arm Cortex -M23 with:
- Single-cycle hardware multiplier
- Hardware divider
- Nested Vector Interrupt Controller (NVIC)
- Memory Protection Unit (MPU)
- Stack Limit Checking
- TrustZone for ARMv8-M (optional)
- Memory:
- 16/32/64-KB Flash
- 4/8/16-KB SRAM
- 2-KB Data Flash Write-While-Read (WWR) section for non-volatile data storage
- 256 bytes TrustRAM with physical protection features
- Clock Management:
- Flexible clock distribution optimized for low power
- 32.768 kHz crystal oscillator
- 32.768 kHz ultra low-power internal RC oscillator
- 0.4 to 32 MHz crystal oscillator
- 16/12/8/4 MHz low-power internal RC oscillator
- Ultra low-power digital Frequency-Locked Loop (DFLLULP)
- 32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)
- One frequency meter
- Low-Power and Power Management:
- Active, Idle, Standby with partial or full SRAM retention and off sleep modes:
- Active mode (<25 μA/MHz)
- Idle mode (<10 μA/MHz) with 1.5 μs wake-up time
- Standby with Full SRAM Retention (0.5 μA) with 5.3 μs wake-up time
- Off mode (<100 nA)
- Static and dynamic power gating architecture
- Sleepwalking peripherals
- Two performance levels
- Embedded Buck/LDO regulator with on-the-fly selection
- Active, Idle, Standby with partial or full SRAM retention and off sleep modes:
- Security:
- Up to four tamper pins for static and dynamic intrusion detections
- Data Flash:
- Optimized for secure storage
- Address and data scrambling with user-defined key (optional)
- Rapid tamper erase on scrambling key and on one user-defined row
- Silent access for data read noise reduction
- TrustRAM:
- Address and data scrambling with user-defined key
- Chip-level tamper detection on physical RAM to resist microprobing attacks
- Rapid tamper erase on scrambling key and RAM data
- Silent access for data read noise reduction
- Data remanence prevention
- Peripherals:
- One True Random Generator (TRNG)
- AES-128, SHA-256, and GCM cryptography accelerators (optional)
- Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with external devices from the non-secure application (optional)
- TrustZone for flexible hardware isolation of memories and peripherals (optional):
- Up to six regions for the Flash
- Up to two regions for the Data Flash
- Up to two regions for the SRAM
- Individual security attribution for each peripheral, I/O, external interrupt line, and Event System Channel
- Secure Boot with SHA-based authentication (optional)
- Up to three debug access levels
- Up to three Chip Erase commands to erase part of or the entire embedded memories
- Unique 128-bit serial number
- SAM L11 Securely Key Provisioned (KPH) (optional):
- Key Provisioning using Root of Trust flow
- Security Software Framework using Kinibi-M Software Development Kit (SDK)
- Advanced Analog and Touch:
- One 12-bit 1 Msps Analog-to-Digital Converter (ADC) with up to 10 channels
- Two Analog Comparators (AC) with window compare function
- One 10-bit 350 ksps Digital-to-Analog Converter (DAC) with external and internal outputs
- Three Operational Amplifiers (OPAMP)
- Up to 20 self-capacitance channels
- Up to 100 (10x10) mutual-capacitance channels
- Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and wheels
- Hardware noise filtering and noise signal desynchronization for high conducted immunity
- Driven Shield Plus for better noise immunity and moisture tolerance
- Parallel Acquisition through Polarity control
- Supports wake-up on touch from Standby Sleep mode
- Communication Interfaces:
- Up to three Serial Communication Interfaces (SERCOM) that can operate as:
- USART with full-duplex and single-wire half-duplex configuration
- I²C up to 3.4 Mbit/s (High-Speed mode) on one instance and up to 1 Mbit/s (Fast-mode Plus) on the second instance
- Serial Peripheral Interface (SPI)
- ISO7816 on one instance (Available on 32-pin packages only)
- RS-485 on one instance (Available on 32-pin packages only)
- LIN Client on one instance (Available on 32-pin packages only)
- Up to three Serial Communication Interfaces (SERCOM) that can operate as:
- Timers/Output Compare/Input Capture:
- Three 16-bit Timers/Counters (TC), each configurable as:
- One 16-bit TC with two compare/capture channels
- One 8-bit TC with two compare/capture channels
- One 32-bit TC with two compare/capture channels, by using two TCs
- PWM Modes using TC peripherals:
- Up to two PWM channels on each 16-bit TC
- 32-bit Real-Time Counter (RTC) with clock/calendar functions
- Watchdog Timer (WDT) with Window mode
- Three 16-bit Timers/Counters (TC), each configurable as:
- Input/Output (I/O):
- Up to 25 programmable I/O lines
- Eight external interrupts (EIC)
- One non-maskable interrupt (NMI)
- One Configurable Custom Logic (CCL) that supports:
- Combinatorial logic functions, such as AND, NAND, OR, and NOR
- Sequential logic functions, such as Flip-Flop and Latches
- Qualification and Class-B Support:
- AEC-Q100 Grade 1 (-40°C to +125°C)
- Class-B safety library, IEC 60730 (future)
- Debugger Development Support:
- Two-pin Serial Wire Debug (SWD) programming and debugging interface
In-Stock: 71
71 In stock, ships now
Add to BOM List
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 4.8655 | $ 4.87 |
| 10+ | $ 4.1368 | $ 41.37 |
| 30+ | $ 3.7037 | $ 111.11 |
| 100+ | $ 3.2658 | $ 326.58 |
| 500+ | $ 3.0635 | $ 1531.75 |
| 1,000+ | $ 2.9718 | $ 2971.80 |
Standard Packaging6000/Full Reel | ||
Better price for more quantity?
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | MICROCHIP | |
| Packaging | QFN-24-EP(4x4) | |
| DAC (Bit) | 10bit | |
| ADC (Bit) | 12bit | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 1.62V~3.63V | |
| Program Memory Type | FLASH | |
| EEPROM | 2KB | |
| Program Storage Size | 32KB | |
| CPU Core | ARM Cortex-M23 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 32MHz | |
| Oscillator Type | Built-in | |
| Number of I/O | 17 |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 6000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Operating Conditions: 1.62V to 3.63V, -40°C to +125°C, DC to 32 MHz
- Core: 32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS) Arm Cortex -M23 with:
- Single-cycle hardware multiplier
- Hardware divider
- Nested Vector Interrupt Controller (NVIC)
- Memory Protection Unit (MPU)
- Stack Limit Checking
- TrustZone for ARMv8-M (optional)
- Memory:
- 16/32/64-KB Flash
- 4/8/16-KB SRAM
- 2-KB Data Flash Write-While-Read (WWR) section for non-volatile data storage
- 256 bytes TrustRAM with physical protection features
- Clock Management:
- Flexible clock distribution optimized for low power
- 32.768 kHz crystal oscillator
- 32.768 kHz ultra low-power internal RC oscillator
- 0.4 to 32 MHz crystal oscillator
- 16/12/8/4 MHz low-power internal RC oscillator
- Ultra low-power digital Frequency-Locked Loop (DFLLULP)
- 32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)
- One frequency meter
- Low-Power and Power Management:
- Active, Idle, Standby with partial or full SRAM retention and off sleep modes:
- Active mode (<25 μA/MHz)
- Idle mode (<10 μA/MHz) with 1.5 μs wake-up time
- Standby with Full SRAM Retention (0.5 μA) with 5.3 μs wake-up time
- Off mode (<100 nA)
- Static and dynamic power gating architecture
- Sleepwalking peripherals
- Two performance levels
- Embedded Buck/LDO regulator with on-the-fly selection
- Active, Idle, Standby with partial or full SRAM retention and off sleep modes:
- Security:
- Up to four tamper pins for static and dynamic intrusion detections
- Data Flash:
- Optimized for secure storage
- Address and data scrambling with user-defined key (optional)
- Rapid tamper erase on scrambling key and on one user-defined row
- Silent access for data read noise reduction
- TrustRAM:
- Address and data scrambling with user-defined key
- Chip-level tamper detection on physical RAM to resist microprobing attacks
- Rapid tamper erase on scrambling key and RAM data
- Silent access for data read noise reduction
- Data remanence prevention
- Peripherals:
- One True Random Generator (TRNG)
- AES-128, SHA-256, and GCM cryptography accelerators (optional)
- Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with external devices from the non-secure application (optional)
- TrustZone for flexible hardware isolation of memories and peripherals (optional):
- Up to six regions for the Flash
- Up to two regions for the Data Flash
- Up to two regions for the SRAM
- Individual security attribution for each peripheral, I/O, external interrupt line, and Event System Channel
- Secure Boot with SHA-based authentication (optional)
- Up to three debug access levels
- Up to three Chip Erase commands to erase part of or the entire embedded memories
- Unique 128-bit serial number
- SAM L11 Securely Key Provisioned (KPH) (optional):
- Key Provisioning using Root of Trust flow
- Security Software Framework using Kinibi-M Software Development Kit (SDK)
- Advanced Analog and Touch:
- One 12-bit 1 Msps Analog-to-Digital Converter (ADC) with up to 10 channels
- Two Analog Comparators (AC) with window compare function
- One 10-bit 350 ksps Digital-to-Analog Converter (DAC) with external and internal outputs
- Three Operational Amplifiers (OPAMP)
- Up to 20 self-capacitance channels
- Up to 100 (10x10) mutual-capacitance channels
- Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and wheels
- Hardware noise filtering and noise signal desynchronization for high conducted immunity
- Driven Shield Plus for better noise immunity and moisture tolerance
- Parallel Acquisition through Polarity control
- Supports wake-up on touch from Standby Sleep mode
- Communication Interfaces:
- Up to three Serial Communication Interfaces (SERCOM) that can operate as:
- USART with full-duplex and single-wire half-duplex configuration
- I²C up to 3.4 Mbit/s (High-Speed mode) on one instance and up to 1 Mbit/s (Fast-mode Plus) on the second instance
- Serial Peripheral Interface (SPI)
- ISO7816 on one instance (Available on 32-pin packages only)
- RS-485 on one instance (Available on 32-pin packages only)
- LIN Client on one instance (Available on 32-pin packages only)
- Up to three Serial Communication Interfaces (SERCOM) that can operate as:
- Timers/Output Compare/Input Capture:
- Three 16-bit Timers/Counters (TC), each configurable as:
- One 16-bit TC with two compare/capture channels
- One 8-bit TC with two compare/capture channels
- One 32-bit TC with two compare/capture channels, by using two TCs
- PWM Modes using TC peripherals:
- Up to two PWM channels on each 16-bit TC
- 32-bit Real-Time Counter (RTC) with clock/calendar functions
- Watchdog Timer (WDT) with Window mode
- Three 16-bit Timers/Counters (TC), each configurable as:
- Input/Output (I/O):
- Up to 25 programmable I/O lines
- Eight external interrupts (EIC)
- One non-maskable interrupt (NMI)
- One Configurable Custom Logic (CCL) that supports:
- Combinatorial logic functions, such as AND, NAND, OR, and NOR
- Sequential logic functions, such as Flip-Flop and Latches
- Qualification and Class-B Support:
- AEC-Q100 Grade 1 (-40°C to +125°C)
- Class-B safety library, IEC 60730 (future)
- Debugger Development Support:
- Two-pin Serial Wire Debug (SWD) programming and debugging interface
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991A2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |