RENESAS 14235R-2000

The FT 5000 Smart Transceiver includes three independent 8-bit logical processors to manage the physical MAC layer, the network, and the user application. These are called the Media-Access Control (MAC) processor, the network (NET) processor, and the application (APP) processor, respectively. At higher system clock rates, there is also a fourth processor to handle interrupts. The FT 5000 Smart Transceiver supports polarity-insensitive cabling using a star, bus, daisy-chain, loop, or combination topology. Thus, installers don't have to follow a strict set of wiring rules imposed by other networking technologies. Instead, they can install wiring in the fastest and most cost-effective manner, thereby saving time and money. Free topology wiring also simplifies network expansion by eliminating restrictions on wire routing, splicing, and device placement. The FT-X3 Communications Transformer is a surface mount communications transformer that's compatible with both the FT 5000 Smart Transceiver and the previous-generation FT 3120/FT 3150 Smart Transceivers. The FT-X3 Communications Transformer provides equivalent noise immunity to both the FT-X1 and FT-X2 Communication Transformers, the previous-generation communication transformers. However, the FT-X3 Communications Transformer is not pin-compatible with the FT-X2 Communication Transformer (which is also a surface mount transformer). The FT 5000 Smart Transceiver can also be used with the FT-X1 and FT-X2 Communication Transformers.

• 3.3V operation.
• Higher-performance Neuron Core—internal system clock scales up to 80MHz.
• Substantial device price reduction.
• Serial memory interface for inexpensive external EEPROM and flash non-volatile memories.
• Supports up to 254 Network Variables (NVs) and 127 aliases.
• Low-cost surface mount FT-X3 Communications Transformer.
• User-programmable interrupts provide faster response time to external events.
• Includes hardware UART with 16-byte receive and transmit FIFOs.
• 7 mm x 7 mm 48-pin QFN package.
• Supports polarity-insensitive free topology star, daisy chain, bus, loop, or mixed topology wiring.
• Compliant with TP/FT-10 channels using FT 3120/FT 3150/Smart Transceivers and FTT-10/FTT-10A/LPT-10/LPT-11 Transceivers.
• 12 I/O pins with 35 programmable standard I/O models.
• Supports up to 42KB of application code space.
• 64KB RAM (44KB user-accessible) and 16KB ROM on-chip memories.
• Unique 48-bit Neuron ID in every device for network installation and management.
• Very high common-mode noise immunity.
• -40°C to +85°C operating temperature range.