ISSI IS46TR16128A-15HBLA1-TR
| Manufacturer | |
| MPN | IS46TR16128A-15HBLA1-TR |
| LCSC Part # | C20425885 |
| Packaging | 96-TWBGA (9x13) |
| Customer # | |
| Key Attributes | 96-TWBGA (9x13) Memory (ICs) RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | ISSI | |
| Packaging | 96-TWBGA (9x13) | |
| Features | Auto self-refresh;Asynchronous reset function;Auto precharge function;Write leveling function;Dynamic on-chip termination;ZQ calibration function;Data mask function |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This article provides detailed information on 256Mx8 and 128Mx16 2Gb DDR3 SDRAM, covering its features such as standard voltage, low voltage, high-speed data transfer rates, 8 internal memory banks, 8n-bit prefetch architecture, and programmable CAS latency. It also describes various configuration, packaging, and refresh interval options, along with the DDR3 package pin layout and functional descriptions — including the reset and initialization process, with specific steps and requirements for the power-on initialization sequence.
Features
- Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
- Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, - 0.067V, backward compatible with 1.5V
- High-speed data transfer rates, system frequency up to 933MHz
- 8 internal banks for concurrent operation
- 8n-bit prefetch architecture
- Programmable CAS latency
- Programmable additive latency: 0, CL - 1, CL - 2
- tCK-based programmable CAS write latency (CWL)
- Programmable burst length: 4 and 8
- Programmable burst sequence: sequential or interleaved
- Dynamic burst length switching
- Auto Self-Refresh (ASR)
- Self-Refresh Temperature (SRT)
- Configurations: 256Mx8, 128Mx16
- Package: 96-ball FBGA (9mm x 13mm) for x16, 78-ball FBGA (8mm x 10.5mm) for x8
- Refresh interval: 7.8μs (8192 cycles/64ms), Tc = - 40°C to 85°C; 3.9μs (8192 cycles/32ms), Tc = 85°C to 105°C
- Partial array self-refresh
- Asynchronous reset pin
- TDQS (Termination Data Strobe) support (x8 only)
- OCD (Off-Chip Driver impedance adjustment)
- Dynamic ODT (On-Die Termination)
- Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
- Write leveling calibration
- Up to 200MHz in DLL-off mode
- Operating temperature: Commercial (Tc = 0°C to + 95°C); Industrial (Tc = - 40°C to + 95°C); Automotive, A1 (Tc = - 40°C to + 95°C); Automotive, A2 (Tc = - 40°C to + 105°C)
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 25.799 | $ 25.80 |
| 200+ | $ 10.2947 | $ 2058.94 |
| 500+ | $ 9.9499 | $ 4974.95 |
| 1,500+ | $ 9.7813 | $ 14671.95 |
Standard Packaging1500/Full Bag | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | ISSI | |
| Packaging | 96-TWBGA (9x13) | |
| Features | Auto self-refresh;Asynchronous reset function;Auto precharge function;Write leveling function;Dynamic on-chip termination;ZQ calibration function;Data mask function |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This article provides detailed information on 256Mx8 and 128Mx16 2Gb DDR3 SDRAM, covering its features such as standard voltage, low voltage, high-speed data transfer rates, 8 internal memory banks, 8n-bit prefetch architecture, and programmable CAS latency. It also describes various configuration, packaging, and refresh interval options, along with the DDR3 package pin layout and functional descriptions — including the reset and initialization process, with specific steps and requirements for the power-on initialization sequence.
Features
- Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
- Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, - 0.067V, backward compatible with 1.5V
- High-speed data transfer rates, system frequency up to 933MHz
- 8 internal banks for concurrent operation
- 8n-bit prefetch architecture
- Programmable CAS latency
- Programmable additive latency: 0, CL - 1, CL - 2
- tCK-based programmable CAS write latency (CWL)
- Programmable burst length: 4 and 8
- Programmable burst sequence: sequential or interleaved
- Dynamic burst length switching
- Auto Self-Refresh (ASR)
- Self-Refresh Temperature (SRT)
- Configurations: 256Mx8, 128Mx16
- Package: 96-ball FBGA (9mm x 13mm) for x16, 78-ball FBGA (8mm x 10.5mm) for x8
- Refresh interval: 7.8μs (8192 cycles/64ms), Tc = - 40°C to 85°C; 3.9μs (8192 cycles/32ms), Tc = 85°C to 105°C
- Partial array self-refresh
- Asynchronous reset pin
- TDQS (Termination Data Strobe) support (x8 only)
- OCD (Off-Chip Driver impedance adjustment)
- Dynamic ODT (On-Die Termination)
- Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
- Write leveling calibration
- Up to 200MHz in DLL-off mode
- Operating temperature: Commercial (Tc = 0°C to + 95°C); Industrial (Tc = - 40°C to + 95°C); Automotive, A1 (Tc = - 40°C to + 95°C); Automotive, A2 (Tc = - 40°C to + 105°C)
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |

