Infineon S6J311DJACSE20000

The S6J3110 series is a set of 32-bit microcontrollers designed for in-vehicle use. It uses the Arm Cortex-R5 CPU as a CPU.

• 32-bit Arm architecture
• 2-instruction issuance super scalar
• 8-stage pipeline
• ECC support for the TCM ports for RAM, 1-bit error correction and 2-bit error detection (SEC-DED)
• 2 TCM ports: ATCM port, BTCM port (B0TCM, B1TCM)
• Instruction cache 16 KB
• Data cache 16 KB
• VIC port: Low latency interrupt
• 64-bit AXI interface (instruction/data access)
• 32-bit AXI interface (I/O access)
• 64-bit AXI interface (TCM port access)
• ETM-R5 trace
• Main clock oscillation (4 MHz)
• No sub clock oscillation
• CR oscillation (100 kHz)
• CR oscillation (4 MHz)
• Program: 4096 K + 64 KB (S6J311EyzC*) / 3072K + 64KB (S6J311DyAC*)
• Work: 112 KB (S6J311EyzC*) / 112 KB (S6J311DyAC*)
• TCRAM 64 KB
• System SRAM 256 KB (S6J311EyzC*) / 192 KB (S6J311DyAC*)
• Backup RAM 64 KB (S6J311EyzC*) / 64 KB (S6J311DyAC*)
• General-purpose ports: 150 channels (S6J311xJAC*)/116 channels (S6J311xHzC*)
• DMA controller: Up to 16 channels can be activated simultaneously.
• A/D converter (successive approximation type): 12-bit resolution, 2 units mounted: Max 64 channels (32 channels + 32 channels)
• External interrupt input: 16 channels, Level ("H"/"L") and edge (rising/falling) can be detected.
• Multi-function serial (transmission and reception FIFOs mounted): Max 22 channels
• <I2C>: Full-duplex double buffering system, 64-byte transmission FIFO, 64-byte reception FIFO. Standard mode (Max. 100kbps) is supported only. DMA transfer is supported (only for ch.0 to ch.7).
• <UART (asynchronous serial interface)>: Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO. Parity check can be enabled/disabled. Built-in dedicated baud rate generator. An external clock can be used as a transfer clock. Parity, frame, overrun error detection functions are available. DMA transfer is supported (only for ch.0 to 7).
• <CSIO (synchronous serial interface)>: Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO. Support for SPI. Both master and slave roles are supported. Data length in bits can be set to a value from 5 to 16 or one of the values of 20, 24, and 32. Built-in dedicated baud rate generator (master operation). External clock input is enabled (slave operation). Overrun error detection function is available. DMA transfer is supported (only for ch.0 to ch.7). Serial chip select SPI function
• <LIN-UART (asynchronous serial interface for LIN)>: Full duplex, double buffering system; 64-byte transmission FIFO, 64-byte reception FIFO. Support for LIN protocol revision 2.1. Both master and slave roles are supported. Framing error and overrun error detection. LIN Synch break generation and detection, LIN Synch Delimiter generation. Built-in dedicated baud rate generator. The external clock can be adjusted by the reload counter. DMA transfer is supported (only for ch.0 to ch.7).
• CAN controller: CAN-FD Max 2 channel. CAN-FD (V3.2.0). CAN transfer speed: 1Mbps. CAN Clock: Max 40MHz. 192 message buffers/channel (reception message buffer size). 32 message buffer/channel (transmission message buffer size)
• Base timer: MAX 30 channels. 16-bit Timer. It is selectable by 4 functions of the PWM/PPG/PWC/Reload Timer. 2-channel cascade connection enables operation as a 32-bit timer.(PWC and Reload Timer)
• Free-run timer: Max 6 channels. 32-bit Timer. Main clock oscillation and CR oscillation are available. Free-run timer output can work in combination with an input capture and an output compare.
• Input capture: Max 12 channels. 32-bit Timer.
• Output compare: Max 12 channels. 32-bit Timer.
• Real time clock (RTC) (day/hour/minute/second). Main clock oscillation or CR oscillation (100 kHz) can be selected as an operation clock.
• Calibration: Real time clock (RTC) driven by the CR clock. Correction can be done by configuring the prescaler of the real time clock based on the ratio between the main clock and the CR clock.
• Clock supervisor: Abnormality (such as damaged crystal) of the main clock oscillation (4 MHz) can be monitored. The clock can switch to the CR clock when an abnormality is detected. PLL abnormality can be detected.
• CRC generation: Fixed-length CRC. CCITT CRC16 generator polynomial: 0x1021. IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
• Watchdog timer: Hardware watchdog. Software watchdog
• NMI
• I/O relocation: Peripheral function pin locations can be changed.
• Low-power consumption control: Standby function. Power-off function. Partial wakeup function