Lattice LFCPNX-100-8LFG672C
| Manufacturer | |
| MPN | LFCPNX-100-8LFG672C |
| LCSC Part # | C19979125 |
| Packaging | FCBGA-672(27x27) |
| Customer # | |
| Key Attributes | FCBGA-672(27x27) FPGAs (Field Programmable Gate Array) RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Manufacturer | Lattice | |
| Packaging | FCBGA-672(27x27) |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 40 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The CertusPro-NX series FPGAs are built on the Lattice Nexus platform, manufactured in 28 nm FD-SOI process, delivering low power consumption and high reliability. The series offers 17K to 100K LUTs, supporting up to 7.2 Mb of embedded memory and 240 18×18 multipliers. They integrate hard-core PCIe and SGMII interfaces, supporting serial transceivers at up to 5.0 Gbps. These FPGAs provide flexible I/O support, including MIPI D-PHY, LVDS, and DDR3 memory interfaces. The architecture incorporates programmable functional units, sysDSP blocks, sysMEM blocks, and advanced clock resources. The series supports secure boot, AES-256 encryption, and single-event upset mitigation, making it suitable for applications demanding high performance and low power consumption.
Features
- Lattice Nexus platform based on 28 nm FD-SOI process
- 17K to 100K 4-input LUTs
- Up to 7.2 Mb embedded memory blocks
- Up to 240 18×18 multipliers
- Hard-core PCIe endpoint supporting Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps)
- Hard-core SGMII interface supporting 10/100/1000 Mbps Ethernet
- Serial transceivers up to 5.0 Gbps
- MIPI D-PHY (1.5 Gbps) and LVDS (up to 1.6 Gbps) interface support
- DDR3 (up to 1066 Mbps) and LPDDR3 (up to 800 Mbps) memory support
- Programmable sysI/O supporting multiple I/O standards
- Integrated 12-bit 1 Msps ADC
- Integrated continuous-time comparator
- Secure boot and AES-256 encryption/decryption support
- Single event upset (SEU) detection and correction
- User-accessible I²C bus
- On-chip oscillator and PLL
- IEEE 1149.1 boundary scan test compliance
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 119.2788 | $ 119.28 |
| 200+ | $ 47.593 | $ 9518.60 |
| 480+ | $ 46.0034 | $ 22081.63 |
| 1,000+ | $ 45.2165 | $ 45216.50 |
Standard Packaging40/Full Tray | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Manufacturer | Lattice | |
| Packaging | FCBGA-672(27x27) |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 40 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The CertusPro-NX series FPGAs are built on the Lattice Nexus platform, manufactured in 28 nm FD-SOI process, delivering low power consumption and high reliability. The series offers 17K to 100K LUTs, supporting up to 7.2 Mb of embedded memory and 240 18×18 multipliers. They integrate hard-core PCIe and SGMII interfaces, supporting serial transceivers at up to 5.0 Gbps. These FPGAs provide flexible I/O support, including MIPI D-PHY, LVDS, and DDR3 memory interfaces. The architecture incorporates programmable functional units, sysDSP blocks, sysMEM blocks, and advanced clock resources. The series supports secure boot, AES-256 encryption, and single-event upset mitigation, making it suitable for applications demanding high performance and low power consumption.
Features
- Lattice Nexus platform based on 28 nm FD-SOI process
- 17K to 100K 4-input LUTs
- Up to 7.2 Mb embedded memory blocks
- Up to 240 18×18 multipliers
- Hard-core PCIe endpoint supporting Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps)
- Hard-core SGMII interface supporting 10/100/1000 Mbps Ethernet
- Serial transceivers up to 5.0 Gbps
- MIPI D-PHY (1.5 Gbps) and LVDS (up to 1.6 Gbps) interface support
- DDR3 (up to 1066 Mbps) and LPDDR3 (up to 800 Mbps) memory support
- Programmable sysI/O supporting multiple I/O standards
- Integrated 12-bit 1 Msps ADC
- Integrated continuous-time comparator
- Secure boot and AES-256 encryption/decryption support
- Single event upset (SEU) detection and correction
- User-accessible I²C bus
- On-chip oscillator and PLL
- IEEE 1149.1 boundary scan test compliance
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991D |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991D |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |

