LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
GR CD4052S product image
  • CD4052S thumbnail 1
  • CD4052S thumbnail 2
  • CD4052S thumbnail 3
  • Pinout
  • Footprint
Images for reference only

GR CD4052SRoHS

Manufacturer
GRAsian Brands
MPN
CD4052S
LCSC Part #
C19818880
Packaging
SOP-16
Customer #
Key Attributes
Two-channel differential four-channel multiplexer
Datasheetpdf iconGR CD4052S
In-Stock: 2,140
2,140 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
5+$ 0.0955$ 0.48
50+$ 0.0764$ 3.82
150+$ 0.0668$ 10.02
500+$ 0.0597$ 29.85
2,500+$ 0.0539$ 134.75
4,000+$ 0.0511$ 204.40
Standard Packaging4000/Full Reel
Better price for more quantity?
$

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Interface/Analog Switches, Multiplexers, Demultiplexers
ManufacturerGR
PackagingSOP-16
FeaturesGlitch-free switching
Operating Temperature0℃~+60℃
Voltage - Supply3V~15V
Ron85Ω@10V
Number of Channels4
Con0.2pF

Additional Information

TypeDetails
Minimum5
Multiple5
Standard Packaging4000
Sales UnitPiece

Introduction

AI Translation

CD4052 is a dual differential 4-channel multiplexer designed with advanced CMOS technology. It is an analog switch in a single-pole, 4-throw configuration, featuring two binary channel control inputs (A and B) and an enable input INH. The two binary input signals simultaneously control the activation of one of the four channels in each switch, while the remaining channels are turned off.

Features

AI Translation
  • Low input current: IIN ≤ 1μA (VIN = VDD - VSS = 15V, Ta = 25°C)
  • Low quiescent current: IDD = 0.2μA (typ.) (VDD - VSS = 15V, Ta = 25°C)
  • Low on-resistance: 60Ω (typ.) (VDD - VSS = VDD - VEE = 15V, Ta = 25°C)
  • Channel leakage current: ±100nA (typ.) (VDD - VEE = 15V)
  • Wide supply voltage VDD - VSS range: 3V ~ 15V
  • Break-before-make switching eliminates channel re-selection overlap
  • SP4T analog switch configuration
  • Package: DIP16, SOP16

Applications

AI Translation
  • Analog and digital multiplexing and demultiplexing
  • Logic level translation for digitally addressed signals
  • Signal gating