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XBLW SN74HC157N(XBLW) product image
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XBLW SN74HC157N(XBLW)RoHS

Manufacturer
XBLWAsian Brands
MPN
SN74HC157N(XBLW)
LCSC Part #
C19708124
Packaging
DIP-16
Customer #
Key Attributes
Quad 2-input Multiplexer
Datasheetpdf iconXBLW SN74HC157N(XBLW)
In-Stock: 362
362 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 0.4014$ 0.3613$ 0.36
10+$ 0.3169$ 0.2853$ 2.85
25+$ 0.2822$ 0.2540$ 6.35
100+$ 0.2369$ 0.2133$ 21.33
500+$ 0.2173$ 0.1956$ 97.80
1,000+$ 0.2052$ 0.1847$ 184.70
Standard Packaging25/Full Tube
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Signal Switches, Multiplexers, Decoders
ManufacturerXBLW
PackagingDIP-16
TypeMultiplexer
Number of Channels8/4
Voltage - Supply2V~6V
Operating Temperature-40℃~+105℃
Features-
Quiescent Current8uA
Current - Output High(IOH)5.2mA
Propagation Delay10ns@6.0V,50pF
Current - Output Low(IOL)5.2mA

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging25
Sales UnitPiece

Introduction

AI Translation

The SN74HC157 is a quad 2-input multiplexers which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the SN74HC157. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The SN74HC157 is logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to S. The logic equations are: 1Y = E(overline) x (1I1 x S + 1I0 x S(overline)) 2Y = E(overline) x (2I1 x S + 2I0 x S(overline)) 3Y = E(overline) x (3I1 x S + 3I0 x S(overline)) 4Y = E(overline) x (4I1 x S + 4I0 x S(overline))

Features

AI Translation
  • Low-power dissipation
  • Non-inverting data path
  • Specified from -40℃ to +105℃
  • Packaging information: DIP-16/SOP-16/TSSOP-16