IC Plus IP1810I

IP1810I is a non-blocking, store-and-forward architecture switch controller, which builds 8-port 10/100Mbps Fast Ethernet MAC and PHY, 1-port GMAC with RGMII interface and 1-port with RGMII/MII for external CPU in a single chip. IP1810I embeds a 4Mb SRAM for the use of packet buffer. It also provides various 2-wire interfaces, such as CPU interface, SMI, and EEPROM interface, which allow the user to access the internal register, external PHY’s registers and EEPROM data. The serial LED can show the status of each port (such as Link, Speed, Activity and so on) by using 74HC164 or IP403 external device through 2-wire (LEDCLK, LEDDAT) signals driving from IP1810I. For avoiding loop occur, IP1810I supports STP, RSTP and MSTP. Even a hardware loop detection mechanism is supported. There are 16K entries in Lookup table. Hashing method can be selected either direct or CRC hashing for MAC address learning. Lookup Table aging time can be adjustable ranging from 55 seconds to 500 hours. IP1810I also provides the MAC learning threshold to limit the number of addresses learning. An independent Multicast table supports 256 entries. For the Internet Group Management Protocol, IP1810I supports IGMP v1/v2/v3 for IPv4 and MLD v1/v2 for IPv6 packet snooping and aging ti

• 8-Port 10/100Mb + 2-Port 10/100/1000Mb Ethernet Switch - Built-in 8 10/100Mb PHYs - RGMII interface for 1 10/100/1000Mb PHYs - RGMII/MII interface for external CPU - Support IEEE802.3az - Support 10/100Mb full/half duplex - Support 1000Mb full duplex - 100Mb TP and Fiber dual mode, selected by Signal Detection (SD) level
• Store & Forward, Share Memory Non-blocking Architecture - Built-in 4Mb SRAM for packet buffer - Support 16K Jumbo packet - Max. length 1664B without supporting jumbo packet
• Wire-Speed Operation On Every Port
• Head Of Line Blocking Prevention
• Flow Control - 802.3x compliant flow control in full duplex - Collision/Carrier_ sense based backpressure in half duplex
• Internal 16K MAC Address Entities - CRC/Direct hashing algorithm - Aging timer programmable (55s~500hrs) - Wire speed address learning and resolution - CPU accessible for security and static MAC - Learning enable/disable
• IGMP/MLD Snooping - IGMP Version 1, 2, 3 / MLD Version 1, 2 - MLD snooping. ( 4 sets IP address per MLD list ) - Snooping by Switch ASIC or CPU
• Two Trunk Group - Two trunk groups, trunk A~B up to 4 ports - Load balance based on (Port ID, DA, SA, DA/SA, IP, TCP/UTP) - Link fault recovery
• Per Port 41 MIB Counters/port - RMON/ Ethernet/ MIB II
• Hardware Auto loop detection
• 10 Port based
• 4K Tag based
• Support Tag remove/add/modify
• IVL/SVL learning mode
• Support Protocol VLAN
• Support Q-in-Q (double tag)
• 64 configurable VID for Q-in-Q tag stacking
• Support FIFS/SP/WRR/SP + WRR/WFQ/TWRR in Output Queue Schedule Modes Port based priority 802.1Q priority tag based IP TOS based (IPv4/IPv6) TCP/UDP port number based Source MAC address based ACL based Privilege priority
• 8 levels per port
• DSCP/ TAG priority remarking 802.1Qad PCP, DEN insert / modify 802.1Q PCP, CFI insert/ modify RX &TX Priority re-mapping LLQ + latency
• 256 levels resolution for all storm control Storm control can be enabled for per port With option to drop all ARP to CPU Unit time can be selected for all storm control
• Ingress、egress、ingress/egress methods
• Two Sniffer destination port group configurations
• Add/ Remove Tag option for packet routing to mirroring ports
• ACL and special tag for sniffer application
• Port Security - MAC based TCP/UDP port based SIP based 802.1x Port based
• From 64K bps to wire speed (resolution 64k)
• Support Flow control on/off Queue based bandwidth control (resolution 64k/1M/2M/4M)
• Speed, Duplex, Flow control, Link CPU accessible and interrupt CPU R/W PHY register Support MMD access
• Frame buffer/ queue/ port based aging
• Bandwidth assured/ limited
• Latency assured
• WRED(Weight Random Early Drop)
• Support LLQ (Low latency queue)
• Dorm mode (WAN/LAN dual schedule mode)
• Support Discard/Block/Learning/Forwarding four states
• Forwarding STP frame to CPU port
• Support RSTP/MSTP
• 128 ACL Entities
• Ingress port
• VLAN
• Destination/Source MAC address
• Destination/Source IP (specific or range) TCP/UDP Destination/Source port number (specific or range)
• IP protocol, DSCP, TCP flag
• Action : forward, to CPU, drop, priority, Q-in-Q tag, remarking, redirect, bandwidth limited
• Pin initial setting
• 2-wire serial interface for accessing EEPROM
• Advanced EEPROM program mode
• 2-wire serial interface for low cost smart system application
• Programmable serial LED Display Function
• OAM (IEEE 802.3 ah) - Auto discovery - Fault indication - Remote LoopBack test
• IEEE1588 stamp - 16 time stamps for Ingress/Egress per port - 8 time stamps for input event trigger - Support Event trigger stamp - Support Pulse Per Second (PPS) output - Support PTP trigger out
• IC+ Remote Management Protocol (IRMP)
• Build-in SRAM Self Test (BIST)
• sFlow
• EoC cable failure auto detection and isolation hardware
• L3/L2 Protocol packets forwarding to CPU or broadcast or drop - LACP,LLDP,IGMP,MLD,ICMP,BPDU,802.1x, GARP
• IPv6 function - TCP/UDP port number and FLAG - Finding out next header is based on ICMPv6, authentication, encapsulation, fragment or user-defined header
• Only need one 25MHz Crystal
• Adjustable IO voltage - (2.5V~3.3V of RGMII/MII for port 10, 2.0V~3.3V of RGMII for port 9)
• Built-in 2.0V regulator
• 128 LQFP , 129 E-Pad Ground