LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Cart
MICROCHIP AT28LV256-25PC product image
Images for reference only

MICROCHIP AT28LV256-25PC

Manufacturer
MICROCHIP
MPN
AT28LV256-25PC
LCSC Part #
C19470065
Packaging
PDIP-28
Customer #
Key Attributes
256Kbit Parallel Port (Parallel) PDIP-28 Memory
DatasheetMICROCHIP AT28LV256-25PC
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement
Out of Stock
Notify Me
Minimum: 1Multiple: 1Sales Unit: Piece
Add to BOM List
QtyUnit Price(Reference Only)Total Amount
1+$ 24.4691$ 24.47
196+$ 9.7646$ 1913.86
504+$ 9.4384$ 4756.95
994+$ 9.2761$ 9220.44
Standard Packaging14/Full Bag
Better price for more quantity?
$

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory
ManufacturerMICROCHIP
PackagingPDIP-28
Operating Temperature0℃~+70℃
FeaturesHardware write protection function;Built-in error correction code (ECC) function;Software write protection function;Noise suppression function
Memory Size256Kbit
Voltage - Supply3V~3.6V;15mA
Clock Frequency-
Access Time250ns
Data Retention - TDR (Year)10 years
Write Cycle Time(tWC)10ms
Standby Supply Current20uA
InterfaceParallel Port (Parallel)
Write Cycle Endurance10000 times
Help & FeedbackShow similar products (0) >

Introduction

AI Translation
  • The AT28LV256 is a high-performance Electrically Erasable and Programmable Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 200 μA.
  • The AT28LV256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin.
  • It has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.

Features

AI Translation
  • Single 3.0V - 3.6V Supply
  • Fast Read Access Time – 200 ns
  • Automatic Page Write Operation – Internal Address and Data Latches for 64 Bytes – Internal Control Timer
  • Fast Write Cycle Times – Page Write Cycle Time: 10 ms Maximum – 1- to 64-byte Page Write Operation
  • Low Power Dissipation – 15 mA Active Current – 20 μA CMOS Standby Current
  • Hardware and Software Data Protection
  • DATA Polling for End of Write Detection
  • High Reliability CMOS Technology – Endurance: 10,000 Cycles – Data Retention: 10 Years
  • JEDEC Approved Byte-wide Pinout
  • Commercial and Industrial Temperature Ranges