MICROCHIP AT28C64-25PC
| Manufacturer | |
| MPN | AT28C64-25PC |
| LCSC Part # | C19434239 |
| Packaging | PDIP-28 |
| Customer # | |
| Key Attributes | 64Kbit 4.5V~5.5V Parallel Port (Parallel) PDIP-28 Memory (ICs) |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | MICROCHIP | |
| Packaging | PDIP-28 | |
| Memory Size | 64Kbit | |
| Voltage - Supply | 4.5V~5.5V | |
| Operating temperature | 0℃~+70℃ | |
| Features | Built-in error correction code (ECC) function;Hardware write protection function | |
| Data Retention - TDR (Year) | 10 years | |
| Write Cycle Time(tWC) | 1ms | |
| Interface | Parallel Port (Parallel) | |
| Write Cycle Endurance | 10000 times |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 14 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The AT28C64 is a low-power, high-performance 8,192 words by 8-bit nonvolatile electrically erasable and programmable read only memory with popular, easy-to-use features. The device is manufactured with reliable nonvolatile technology. The AT28C64 is accessed like a Static RAM for the read or write cycles without the need for external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. The device includes two methods for detecting the end of a write cycle, level detection of RDY/BUSY (unless pin 1 is N.C.) and DATA Polling of I/O₇. Once the end of a write cycle has been detected, a new access for a read or write can begin. The CMOS technology offers fast access times of 120 ns at low power dissipation. When the chip is deselected the standby current is less than 100 μA. The AT28C64 has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved data retention characteristics. An extra 32 bytes of EEPROM are available for device identification or tracking.
Features
- Fast Read Access Time – 120 ns
- Fast Byte Write – 200 μs or 1 ms
- Self-timed Byte Write Cycle – Internal Address and Data Latches – Internal Control Timer – Automatic Clear Before Write
- Direct Microprocessor Control – READY/BUSY Open Drain Output – DATA Polling
- Low Power – 30 mA Active Current – 100 μA CMOS Standby Current
- High Reliability – Endurance: 10⁴ or 10⁵ Cycles – Data Retention: 10 Years
- 5V ±10% Supply
- CMOS and TTL Compatible Inputs and Outputs
- JEDEC Approved Byte-wide Pinout
- Commercial and Industrial Temperature Ranges
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | MICROCHIP | |
| Packaging | PDIP-28 | |
| Memory Size | 64Kbit | |
| Voltage - Supply | 4.5V~5.5V | |
| Operating temperature | 0℃~+70℃ | |
| Features | Built-in error correction code (ECC) function;Hardware write protection function | |
| Data Retention - TDR (Year) | 10 years | |
| Write Cycle Time(tWC) | 1ms | |
| Interface | Parallel Port (Parallel) | |
| Write Cycle Endurance | 10000 times |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 14 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The AT28C64 is a low-power, high-performance 8,192 words by 8-bit nonvolatile electrically erasable and programmable read only memory with popular, easy-to-use features. The device is manufactured with reliable nonvolatile technology. The AT28C64 is accessed like a Static RAM for the read or write cycles without the need for external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will go to a busy state and automatically clear and write the latched data using an internal control timer. The device includes two methods for detecting the end of a write cycle, level detection of RDY/BUSY (unless pin 1 is N.C.) and DATA Polling of I/O₇. Once the end of a write cycle has been detected, a new access for a read or write can begin. The CMOS technology offers fast access times of 120 ns at low power dissipation. When the chip is deselected the standby current is less than 100 μA. The AT28C64 has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved data retention characteristics. An extra 32 bytes of EEPROM are available for device identification or tracking.
Features
- Fast Read Access Time – 120 ns
- Fast Byte Write – 200 μs or 1 ms
- Self-timed Byte Write Cycle – Internal Address and Data Latches – Internal Control Timer – Automatic Clear Before Write
- Direct Microprocessor Control – READY/BUSY Open Drain Output – DATA Polling
- Low Power – 30 mA Active Current – 100 μA CMOS Standby Current
- High Reliability – Endurance: 10⁴ or 10⁵ Cycles – Data Retention: 10 Years
- 5V ±10% Supply
- CMOS and TTL Compatible Inputs and Outputs
- JEDEC Approved Byte-wide Pinout
- Commercial and Industrial Temperature Ranges
Compliance & Export Codes
| Type | Details |
|---|---|
| ECCN | - |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| ECCN | - |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |

