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QuickLogic V96SSC-33LP product image
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QuickLogic V96SSC-33LP

Manufacturer
MPN
V96SSC-33LP
LCSC Part #
C19311076
Packaging
-
Customer #
Key Attributes
Memory Controllers
Datasheetpdf iconQuickLogic V96SSC-33LP

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory Controllers
ManufacturerQuickLogic
Packaging-
FeaturesInterrupt generation

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging13
Sales UnitPiece

Introduction

AI Translation

The V96SSC High-Integration System Controller is a single-chip device that simplifies the design of systems based on i960Sx i960Jx or PPC401Gx embedded microprocessors. The V96SSC replaces many lower integration components with a single, high-integration device. Beyond simplifying memory and peripheral control, the V96SSC also includes many of the peripherals needed to build a high-performance i960 or PPC401Gx based system: DMA channels, synchronous/asynchronous serial port, general purpose and system heartbeat timers, bit I/O ports, and an interrupt controller. Nearly all i960 or PowerPC processor based systems will require DRAM for code and data storage. The V96SSC includes a high-performance DRAM controller which is programmable to accommodate a wide range of DRAM speeds and architectures. The eight chip-select/strobes further simplify peripheral/memory connection. Each select has programmable timing and a total of four wait state generators are provided. In addition, the V96SSC includes special features to enhance system integrity. The bus watch timer prevents system hangs on access to unpopulated memory. A watchdog timer is also included to recover from software upsets. Due to its small footprint, and glueless interface, the V96SSC provides the best features of an integrated processor without any performance compromises!

Features

AI Translation
  • Direct interface to i960Sx/Jx and PPC401Gx processors
  • High-performance burst DRAM controller
  • Two-channel fly-by DMA controller
  • Serial communications unit
  • Programmable chip-select/strobe generation
  • Support for 8/16-bit boot PROMs
  • Two 32-bit general purpose timers
  • Pulse width modulation capability
  • 16 general purpose I/O bits
  • Eight input ports and eight output ports
  • Interrupt control unit
  • Local bus speeds up to 33MHz
  • Low cost 100-pin EIAJ PQFP package
  • Fastest time to market for i960Sx and i960Jx based designs
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