Infineon CYP15G0402DXB-BGC

The CYP(V)15G0402DXB[1] Quad HOTLink II™ SERDES is a point-to-point communications building block allowing the transfer of preencoded data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud per serial link. Each transmit channel accepts preencoded 10-bit transmission characters in an Input Register, serializes each character, and drives it out a PECL-compatible differential line driver. Each receive channel accepts a serial data stream at a differential line receiver, deserializes the stream into 10-bit characters, optionally frames these characters to the proper 10-bit character boundaries and presents these characters to an Output register. As a second-generation HOTLink device, the CYP(V)15G0402DXB extends the HOTLink family to faster data rates, while maintaining serial link compatibility (data, command and BIST) with other HOTLink devices. The transmit (TX) section of the CYP(V)15G0402DXB Quad HOTLink II SERDES consists of four ten bit wide channels that accept a preencoded character on every clock cycle. Transmission characters are passed from the Transmit Input Register to a Serializer. The serialized characters are output from a differential transmission line driver at a bit-rate of 10 or 20 times the input reference clock. The receive (RX) section of the CYP(V)15G0402DXB Quad HOTLink II SERDES consists of four ten bit wide channels. Each channel accepts a serial bit-stream from a PECL-compatible differential line receiver and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. Each recovered bit-stream is deserialized and framed into characters. Recovered characters are then passed to the receiver output register, along with a recovered character clock. The parallel input interface may be configured for numerous forms of clocking to provide the high flexibility in system architecture. Each transmit and receive channel contains an independent BIST pattern generator and checker. This BIST hardware allows at-speed testing of the interface data path. HOTLink II devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-to-point serial links.

• Second-generation HOTLink technology
• Compliant to multiple standards — Fibre Channel, Gigabit Ethernet (IEEE802.3z), ESCON and DVB-ASI — CYV15G0402DXB compliant to SMPTE 259M and SMPTE 292M
• Quad-channel transceiver operates from 195 to 1500 Mbps serial data rate — Aggregate throughput of 12 Gbps
• 10-bit unencoded data transport
• Selectable parity check/generate
• Four independent 10-bit channels with separate Clock and Data Recovery for each channel
• Selectable input clocking options
• MultiFrame Receive Framer — Comma or full K28.5 detect — Single or Multi-Byte framer for byte alignment — Low-latency option
• Synchronous LVTTL parallel interface
• Internal phase-locked loops (PLLs) with no external PLL components
• Optional Phase Align Buffer in Transmit Path
• Differential PECL-compatible serial inputs
• Differential PECL-compatible serial outputs — Source matched for 50Ω transmission lines — No external resistors required — Signaling rate controlled edge rates
• Compatible with — Fiber-optic modules — Copper cables
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator — Analog signal detect — Digital signal detect
• Low-power 2.5W @3.38 typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb-Free package option available
• 0.25μ BiCMOS technology

• Interconnecting backplanes on switches
• Routers
• Servers
• Video transmission systems