The CY22388 family of devices has an analog VCXO, four PLLs, up to eight clock outputs and frequency selection capabilities. The frequency selects do not modify any PLL frequency. Instead they allow the user to choose among eight different output divider selections depending on the clock and package configuration.
There is one programmable OE/PD#. The OE/PD# pin can be programmed as either an output enable pin or a power-down pin. The OE function can be programmed to disable a selected set of outputs when low, leaving the remaining outputs running. Full-chip power-down disables all outputs and the PLLs and most of the active circuitry when low.
The advantage of having four PLLs is that a single device can generate up to four independent frequencies from a single crystal. Generally a design may require up to four oscillators to accomplish what could be done with a single CY22388.
Each PLL is independent and can be configured to generate a voltage-controlled oscillator (VCO) frequency between 62.5 MHz and 250 MHz. Each PLL can then, in turn, be divided down with post dividers to generate the clock output frequency of the user’s choice. The output divider allows each clock output to be divided by 1, 2, 3, 4, 5, 6, 8, 9, 10, 12 or 15. The PLL maximum is reduced to 166 MHz in ‘divide by 1’ mode due to output buffer limitations.
Outputs that allow frequency switching perform a glitch-free transition. A glitch is defined as a high- or low-time shorter than half the smaller of the two periods being switched between. Extended low time (even many cycles in duration) is acceptable.
Selected clock outputs are capable of being powered off a separate 2.5-V supply. This allows for driving lower voltage swing inputs. The CY22388/89/91 device still requires 3.3 V to power the oscillator and all other internal PLL circuitry. For the 2.5-V output option, refer to the CY22388 application note. Selected clocks and pinout diagrams are explained in this application note.
Clock D can obtain its output from either the reference source or PLL1/N1 with N1 being defined as the output divider for PLL1. Clock H is defined as a copy of clock D. Clock D is only available from PLL1/N1 on the 16-pin package.
For CY22388, CLKB and CLKC have related frequencies. For CY22389 and CY22391, CLKD and CLKF have related frequencies, CLKA and CLKB have related frequencies, and CLKC and CLKE have related frequencies. Related frequencies come from the same PLL but can have different divider values.
To minimize parts per million (PPM) error on the clock outputs, you must choose a crystal reference frequency that is a common multiple of the desired PLL frequencies. While this is the ideal situation, this is not always the case and the PLLs have high-resolution counters internally to help minimize frequency deviation from the desired frequency.
PLL VCO frequencies are generated by the following equation: F_VCO = F_REF × (P / Q)
where FREF is the reference input frequency, P is the PLL feedback divider, and Q is the reference input divider.
A PLL is a feedback system where the VCO frequency divided by P and reference frequency divided by Q are constantly being compared and the VCO frequency is adjusted to achieve a locked state.
Infineon CY22391LTXC-06