TI SN74LVC2G08MDCUREP
| Manufacturer | |
| MPN | SN74LVC2G08MDCUREP |
| LCSC Part # | C18150 |
| Packaging | VSON-8(2.3x2.3) |
| Customer # | |
| Key Attributes | DUAL 2-INPUT POSITIVE-AND GATE |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | TI | |
| Packaging | VSON-8(2.3x2.3) | |
| Features | Local shutdown mode | |
| Input Logic Level - Low | 700mV~800mV | |
| Input Logic Level - High | 1.7V~2V | |
| Operating Temperature | -55℃~+125℃ | |
| Logic Family | 74LVC Series | |
| Output Logic Level - High | 1.2V;1.9V;2.4V;2.3V | |
| Quiescent Current(Iq) | 10uA | |
| Voltage - Supply | 1.65V~5.5V | |
| Number of Channels | 2;2 | |
| Current - Output High(IOH) | 24mA | |
| Output Logic Level - Low | 100mV;450mV;300mV;400mV;550mV | |
| Propagation Delay | 4.8ns@5V,50pF | |
| Current - Output Low(IOL) | 24mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V Vcc operation. The SN74LVC2G08 performs the Boolean function Y = A • B or Y = ¬(¬A + ¬B) in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Controlled Baseline
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- Supports 5-V Vcc Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 5.7 ns at 3.3 V
- Low Power Consumption, 10 μA Max Icc
- ±24 mA Output Drive at 3.3 V
- Typical VoLP (Output Ground Bounce) < 0.8 V at VCC = 3.3V, TA = 25°C
- Typical V0HV (Output VoH Undershoot) > 2 V at VCC = 3.3V, TA = 25°C
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD22 - 2000-V Human-Body Model (A114-A), 1000-V Charged-Device Model (C101)
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 2.6772 | $ 2.68 |
| 10+ | $ 2.2685 | $ 22.69 |
| 30+ | $ 2.0107 | $ 60.32 |
| 100+ | $ 1.748 | $ 174.80 |
| 500+ | $ 1.6297 | $ 814.85 |
| 1,000+ | $ 1.5794 | $ 1579.40 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | TI | |
| Packaging | VSON-8(2.3x2.3) | |
| Features | Local shutdown mode | |
| Input Logic Level - Low | 700mV~800mV | |
| Input Logic Level - High | 1.7V~2V | |
| Operating Temperature | -55℃~+125℃ | |
| Logic Family | 74LVC Series | |
| Output Logic Level - High | 1.2V;1.9V;2.4V;2.3V | |
| Quiescent Current(Iq) | 10uA | |
| Voltage - Supply | 1.65V~5.5V | |
| Number of Channels | 2;2 | |
| Current - Output High(IOH) | 24mA | |
| Output Logic Level - Low | 100mV;450mV;300mV;400mV;550mV | |
| Propagation Delay | 4.8ns@5V,50pF | |
| Current - Output Low(IOL) | 24mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V Vcc operation. The SN74LVC2G08 performs the Boolean function Y = A • B or Y = ¬(¬A + ¬B) in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Controlled Baseline
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- Supports 5-V Vcc Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 5.7 ns at 3.3 V
- Low Power Consumption, 10 μA Max Icc
- ±24 mA Output Drive at 3.3 V
- Typical VoLP (Output Ground Bounce) < 0.8 V at VCC = 3.3V, TA = 25°C
- Typical V0HV (Output VoH Undershoot) > 2 V at VCC = 3.3V, TA = 25°C
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD22 - 2000-V Human-Body Model (A114-A), 1000-V Charged-Device Model (C101)
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



