TI DP8429VX-70

The DP8428 and DP8429 1M DRAM Controller/Drivers are designed to provide "No-Waitstate' CPU interface to Dynamic RAM arrays of up to 8 Mbytes and larger. The DP8428 and DP8429 are tailored for 32-bit and 16-bit system requirements, respectively. Both devices are fabricated using National's new oxide isolated Advanced Low power Schottky (ALS) process and use design techniques which enable them to significantly out-perform all other LSl or discrete alternatives in speed, level of integration, and power consumption. Each device integrates the following critical 1M DRAM controller functions on a single monolithic device: ultra precise delay line; 9 bit refresh counter; fall-through row, column, and bank select input latches; Row/Column address muxing logic; on-board high capacitive-load RAS, CAS, Write Enable and Address output drivers; and, precise control signal timing for all the above. With its four independent RAS outputs and ten multiplexed address outputs, the DP8429 can support up to four banks of 64k, 256k or 1M DRAMs. Two bank select pins, B1 and B0, are decoded to activate one of the RAS signals during an access, leaving the three non-selected banks in the standby mode (less than one tenth of the operating power) with data outputs in TRi-STATE. The DP8428's one Bank Select pin, B1, enables 2 banks automatically during an access in order to provide an optimum interface for 32-bit microprocessors. The DP8428 and DP8429 each have two mode-select pins, allowing for two refresh modes and two access modes. Refresh and access timing may be controlled either externally or automatically. The automatic modes require a minimum of input control signals. A refresh counter is on-chip and is multiplexed with the row and column inputs. Its contents appear at the address outputs of the DP8428 or DP8429 during any refresh, and are incremented at the completion of the refresh. Row, Column and bank address latches are also on-chip. However, if the address inputs to the DP8428 or DP8429 are valid throughout the duration of the access, these latches may be operated in the fall-through mode. Each device is available in either the 52 pin Ceramic DiP, or the low cost JEDEC standard 68 pin Plastic Chip Carrier (PCC) package.

• Makes DRAM interface and refresh tasks appear virtually transparent to the CPU making DRAMs as easy to use as static RAMs
• Specifically designed to eliminate CPU wait states up to 10 MHz or beyond
• Eliminates 20 discrete components for significant board real estate reduction, system power savings and the elimination of chip-to-chip AC skewing
• On-board ultra precise delay line
• On-board high capacitive AAS, CAS, WE and Address drivers (specified driving 88 DRAMs directly)
• AC specified for directly addressing up to 8 Mbytes
• Low power/high speed bipolar oxide isolated process
• Downward pin and function compatible with 256k DRAM Controller/Drivers DP8409A, DP8417, DP8418, and DP8419