LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Intel/Altera EPC1064VTC32 product image
Images for reference only

Intel/Altera EPC1064VTC32

Manufacturer
MPN
EPC1064VTC32
LCSC Part #
C17649785
Packaging
TQFP-32(7x7)
Customer #
Key Attributes
64Kbit TQFP-32(7x7) Configuration PROMs for FPGAs
Datasheetpdf iconIntel/Altera EPC1064VTC32

Products Specifications

Show similar products (0) >
TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Configuration PROMs for FPGAs
ManufacturerIntel/Altera
PackagingTQFP-32(7x7)
FeaturesOutput enable;Power-on reset delay
Memory Size64Kbit
Operating Temperature0℃~+70℃
Voltage - Supply3.3V
Programmable Type-

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging100
Sales UnitPiece

Introduction

AI Translation

With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based Stratix series, Cyclone series, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, and FLEX 6000 devices.

Features

AI Translation
  • Configuration device family for configuring Stratix series, Cyclone series, APEX II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), Mercury, ACEX 1K, and FLEX (FLEX 10KE, and FLEX 10KA) devices
  • Easy-to-use 4-pin interface to Altera FPGAs
  • Low current during configuration and near-zero standby current
  • 5.0-V and 3.3-V operation
  • Software design support with the Altera Quartus II and MAX PLUS II development systems for Windows-based PCs as well as Sun SPARCstation, and HP 9000 Series 700/800
  • Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
  • Available in compact plastic packages: 8-pin plastic dual in-line package (PDIP), 20-pin plastic J-lead chip carrier (PLCC) package, 32-pin plastic thin quad flat pack (TQFP) package
  • EPC2 device has reprogrammable Flash configuration memory
  • 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface
  • Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
  • ISP circuitry is compatible with IEEE Std. 1532
  • Supports programming through Serial Vector Format Files (.svf), Jam Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the Quartus II and MAX + PLUS II software via the USB Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
  • nINIT_CONF pin allows INIT_CONF JTAG instruction to initiate FPGA configuration
  • Can be programmed with Programmer Object Files (.pof) for EPC1 and EPC1441 devices
  • Available in 20-pin PLCC and 32-pin TQFP packages
Out of Stock
Stock Notification
Add to BOM List
QtyUnit Price(Reference Only)Total Amount
1+$ 1.6746$ 1.67
200+$ 0.6683$ 133.66
500+$ 0.6467$ 323.35
1,000+$ 0.6359$ 635.90
Standard Packaging100/Full Bag
Better price for more quantity?
$