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ISSI IS46TR16640ED-15HBLA1-TR product image
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ISSI IS46TR16640ED-15HBLA1-TRRoHS

Manufacturer
MPN
IS46TR16640ED-15HBLA1-TR
LCSC Part #
C17535284
Packaging
TWBGA-96(9x13)
Customer #
Key Attributes
1Gbit 1.425V~1.575V 666.5MHz DDR3 SDRAM TWBGA-96(9x13) Memory (ICs) RoHS
Datasheetpdf iconISSI IS46TR16640ED-15HBLA1-TR
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QtyUnit Price(Reference Only)Total Amount
1+$ 14.1926$ 14.19
200+$ 5.6632$ 1132.64
500+$ 5.474$ 2737.00
1,500+$ 5.3801$ 8070.15
Standard Packaging1500/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory (ICs)
ManufacturerISSI
PackagingTWBGA-96(9x13)
Refresh Current-
Memory Size1Gbit
Voltage - Supply1.425V~1.575V
Operating temperature-40℃~+95℃
Clock Frequency666.5MHz
FeaturesAuto self-refresh;Auto precharge function;Asynchronous reset function;Write leveling function;Dynamic on-chip termination;ZQ calibration function;Data mask function
Memory FormatDDR3 SDRAM
Current - Supply-

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging1500
Sales UnitPiece

Introduction

AI Translation

This article provides detailed information on the 128MX8 and 64MX16 1Gb DDR3 SDRAM with ECC functionality, covering its features, ECC function, options, speed grades, pin assignment descriptions, functional descriptions, and power-on initialization procedures. The power-on initialization must be performed in a specific sequence, including applying power, waiting for RESET# deassertion, starting and stabilizing the clock, and other steps, with corresponding requirements for pin voltages and signal states.

Features

AI Translation
  • Standard voltage: VDD and VDDQ = 1.5V ± 0.075V
  • High-speed data transfer rate, system frequency up to 800 MHz
  • 8 internal banks with concurrent operation
  • 8n-bit prefetch architecture
  • Programmable CAS latency
  • Programmable additive latency: 0, CL - 1, CL - 2
  • tCK-based programmable CAS write latency (CWL)
  • Programmable burst length: 4 and 8
  • Programmable burst sequence: sequential or interleaved
  • Dynamic burst length switching
  • Auto self-refresh (ASR)
  • Self-refresh temperature (SRT)
  • Single-bit error correction (per 64 bits)
  • Restrictions on burst length and data mask
  • Configurations: 128Mx8, 64Mx16
  • Package: 96-ball FBGA (9mm x 13mm) for x16; 78-ball FBGA (8mm x 10.5mm) for x8
  • Refresh interval: 7.8 μs (8192 cycles/64 ms), temperature range -40°C to 85°C; 3.9 μs (8192 cycles/32 ms), temperature range 85°C to 105°C; 1.95 μs (8192 cycles/16 ms), temperature range 105°C to 125°C
  • Partial array self-refresh
  • Asynchronous reset pin
  • TDQS support (termination data strobe, x8 only)
  • OCD (off-chip driver impedance calibration)
  • Dynamic ODT (on-die termination)
  • Driver strength: RZQ/7, RZQ/6 (RZQ = 240 Ω)
  • Write leveling
  • Operating temperature: Automotive grade, A1 (TC = -40°C to +95°C); Automotive grade, A2 (TC = -40°C to +105°C); Automotive grade, A3 (TC = -40°C to +125°C)