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ISSI IS46TR16128DL-125KBLA2 product image
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ISSI IS46TR16128DL-125KBLA2RoHS

Manufacturer
ISSI
MPN
IS46TR16128DL-125KBLA2
LCSC Part #
C17527092
Packaging
TWBGA-96(9x13)
Customer #
Key Attributes
1.283V~1.45V 2Gbit 800MHz DDR3L SDRAM TWBGA-96(9x13) Memory (ICs) RoHS
Datasheetpdf iconISSI IS46TR16128DL-125KBLA2
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QtyUnit Price(Reference Only)Total Amount
1+$ 5.5062$ 5.51
10+$ 4.7645$ 47.65
30+$ 4.3117$ 129.35
100+$ 3.933$ 393.30
Standard Packaging190/Full Tray
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory (ICs)
ManufacturerISSI
PackagingTWBGA-96(9x13)
Voltage - Supply1.283V~1.45V
Memory Size2Gbit
Operating temperature-40℃~+105℃
Clock Frequency800MHz
FeaturesAuto self-refresh;Asynchronous reset function;Auto precharge function;Write leveling function;Dynamic on-chip termination;ZQ calibration function;Data mask function
Memory FormatDDR3L SDRAM
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging190
Sales UnitPiece

Introduction

AI Translation

This document describes the 256Mx8 and 128Mx16 2Gb DDR3 SDRAM, covering its features, configurations, packages, pin descriptions, and reset and initialization procedures. Regarding reset and initialization, it provides detailed coverage of the power-up initialization sequence, including voltage requirements when applying power, reset signal hold time, clock startup and stabilization requirements, as well as the device states and signal settings at various stages.

Features

AI Translation
  • Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
  • Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V
  • Backward compatible to 1.5V
  • High speed data transfer rates with system frequency up to 1066 MHz
  • 8 internal banks for concurrent operation
  • 8n-Bit pre-fetch architecture
  • Programmable CAS Latency
  • Programmable Additive Latency: 0, CL - 1, CL - 2
  • Programmable CAS WRITE latency (CWL) based on tCK
  • Programmable Burst Length: 4 and 8
  • Programmable Burst Sequence: Sequential or Interleave
  • BL switch on the fly
  • Auto Self Refresh(ASR)
  • Self Refresh Temperature (SRT) Refresh Interval: 7.8 µs (8192 cycles/164 ms) TC = -40℃ to 85℃; 3.9 µs (8192 cycles/32 ms) TC = 85℃ to 105℃; 1.95 µs (8192 cycles/16 ms) TC = 105℃ to 115℃; 0.97 µs (8192 cycles/8 ms) TC = 115℃ to 125℃
  • Partial Array Self Refresh
  • Asynchronous RESET pin
  • TDQS (Termination Data Strobe) supported (x8 only)
  • OCD (Off-Chip Driver Impedance Adjustment)
  • Dynamic ODT (On-Die Termination)
  • Driver strength: RZQ/7, RZQ/6 (RZQ = 240 Ω)
  • Write Leveling Up to 200 MHz in DLL off mode
  • Operating temperature: Commercial (ΔTc = 0℃ to +95℃); Industrial (Tc = -40℃ to +95℃); Automotive, A1 (Tc = -40℃ to +95℃); Automotive, A2 (Tc = -40℃ to +105℃); Automotive, A25 (Tc = -40℃ to +115℃); Automotive, A3 (Tc = -40℃ to +125℃)