AMD XCF08PVO48C0973
| Manufacturer | |
| MPN | XCF08PVO48C0973 |
| LCSC Part # | C17507530 |
| Packaging | - |
| Customer # | |
| Key Attributes | Configuration PROMs for FPGAs RoHS |
| Datasheet |  AMD XCF08PVO48C0973 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Configuration PROMs for FPGAs | |
| Manufacturer | AMD | |
| Packaging | - | |
| Features | Daisy chain;Read protection;Sector write protection;Power-on reset delay;Design version storage function;Built-in data decompression function;Output enable |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
Available in 1 to 32 Mb densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial and Slave Serial FPGA configuration modes. The XCFxxP version includes 32 Mb, 16 Mb, and 8 Mb PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes. When driven from a stable, external clock, the PROMs can output data at rates up to 33 MHz. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. With CF High, a short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are both clocked by an external clock source, or optionally, for the XCFxxP PROM only, the PROM can be used to drive the FPGA’s configuration clock. The XCFxxP version of the Platform Flash PROM also supports Master SelectMAP and Slave SelectMAP (or Slave Parallel) FPGA configuration modes. When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave SelectMAP Mode, either an external oscillator generates the configuration clock that drives the PROM and the FPGA, or optionally, the XCFxxP PROM can be used to drive the FPGA’s configuration clock. With BUSY Low and CF High, after CE and OE are enabled, data is available on the PROMs DATA (D0 - D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free - running oscillator can be used in the Slave Parallel/Slave SelectMAP mode. The XCFxxP version of the Platform Flash PROM provides additional advanced features. A built - in data decompressor supports utilizing compressed PROM files, and design revisioning allows multiple design revisions to be stored on a single PROM or stored across several PROMs. For design revisioning, external pins or internal control bits are used to select the active design revision. Multiple Platform Flash PROM devices can be cascaded to support the larger configuration files required when targeting larger FPGA devices or targeting multiple FPGAs daisy chained together. When utilizing the advanced features for the XCFxxP Platform Flash PROM, such as design revisioning, programming files which span cascaded PROM devices can only be created for cascaded chains containing only XCFxxP PROMs. If the advanced XCFxxP features are not enabled, then the cascaded chain can include both XCFxxP and XCFxxS PROMs.
Features
- In-System Programmable PROMs for Configuration of Xilinx FPGAs
- Low-Power Advanced CMOS NOR Flash Process
- Endurance of 20,000 Program/Erase Cycles
- Operation over Full Industrial Temperature Range (-40℃ to +85℃)
- IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing
- JTAG Command Initiation of Standard FPGA Configuration
- Cascadable for Storing Longer or Multiple Bitstreams
- Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
- I/O Pins Compatible with Voltage Levels Ranging From 1.8V to 3.3V
- Design Support Using the Xilinx ISE Alliance and Foundation Software Packages
- 3.3V Supply Voltage (XCF01S/XCF02S/XCF04S)
- Serial FPGA Configuration Interface (XCF01S/XCF02S/XCF04S)
- Available in Small-Footprint VO20 and VOG20 Packages (XCF01S/XCF02S/XCF04S)
- 1.8V Supply Voltage (XCF08P/XCF16P/XCF32P)
- Serial or Parallel FPGA Configuration Interface (XCF08P/XCF16P/XCF32P)
- Available in Small-Footprint VO48, VOG48, FS48, and FSG48 Packages (XCF08P/XCF16P/XCF32P)
- Design Revision Technology Enables Storing and Accessing Multiple Design Revisions for Configuration
- Built-In Data Decompressor Compatible with Xilinx Advanced Compression Technology
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 2.6462 | $ 2.65 |
| 200+ | $ 1.0558 | $ 211.16 |
| 500+ | $ 1.0209 | $ 510.45 |
| 1,000+ | $ 1.0043 | $ 1004.30 |
Standard Packaging1/Full Bag | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Configuration PROMs for FPGAs | |
| Manufacturer | AMD | |
| Packaging | - | |
| Features | Daisy chain;Read protection;Sector write protection;Power-on reset delay;Design version storage function;Built-in data decompression function;Output enable |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
Available in 1 to 32 Mb densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial and Slave Serial FPGA configuration modes. The XCFxxP version includes 32 Mb, 16 Mb, and 8 Mb PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes. When driven from a stable, external clock, the PROMs can output data at rates up to 33 MHz. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. With CF High, a short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are both clocked by an external clock source, or optionally, for the XCFxxP PROM only, the PROM can be used to drive the FPGA’s configuration clock. The XCFxxP version of the Platform Flash PROM also supports Master SelectMAP and Slave SelectMAP (or Slave Parallel) FPGA configuration modes. When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave SelectMAP Mode, either an external oscillator generates the configuration clock that drives the PROM and the FPGA, or optionally, the XCFxxP PROM can be used to drive the FPGA’s configuration clock. With BUSY Low and CF High, after CE and OE are enabled, data is available on the PROMs DATA (D0 - D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free - running oscillator can be used in the Slave Parallel/Slave SelectMAP mode. The XCFxxP version of the Platform Flash PROM provides additional advanced features. A built - in data decompressor supports utilizing compressed PROM files, and design revisioning allows multiple design revisions to be stored on a single PROM or stored across several PROMs. For design revisioning, external pins or internal control bits are used to select the active design revision. Multiple Platform Flash PROM devices can be cascaded to support the larger configuration files required when targeting larger FPGA devices or targeting multiple FPGAs daisy chained together. When utilizing the advanced features for the XCFxxP Platform Flash PROM, such as design revisioning, programming files which span cascaded PROM devices can only be created for cascaded chains containing only XCFxxP PROMs. If the advanced XCFxxP features are not enabled, then the cascaded chain can include both XCFxxP and XCFxxS PROMs.
Features
- In-System Programmable PROMs for Configuration of Xilinx FPGAs
- Low-Power Advanced CMOS NOR Flash Process
- Endurance of 20,000 Program/Erase Cycles
- Operation over Full Industrial Temperature Range (-40℃ to +85℃)
- IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing
- JTAG Command Initiation of Standard FPGA Configuration
- Cascadable for Storing Longer or Multiple Bitstreams
- Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
- I/O Pins Compatible with Voltage Levels Ranging From 1.8V to 3.3V
- Design Support Using the Xilinx ISE Alliance and Foundation Software Packages
- 3.3V Supply Voltage (XCF01S/XCF02S/XCF04S)
- Serial FPGA Configuration Interface (XCF01S/XCF02S/XCF04S)
- Available in Small-Footprint VO20 and VOG20 Packages (XCF01S/XCF02S/XCF04S)
- 1.8V Supply Voltage (XCF08P/XCF16P/XCF32P)
- Serial or Parallel FPGA Configuration Interface (XCF08P/XCF16P/XCF32P)
- Available in Small-Footprint VO48, VOG48, FS48, and FSG48 Packages (XCF08P/XCF16P/XCF32P)
- Design Revision Technology Enables Storing and Accessing Multiple Design Revisions for Configuration
- Built-In Data Decompressor Compatible with Xilinx Advanced Compression Technology
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |