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Advanced Linear Devices ALD310702PCLRoHS

Manufacturer
MPN
ALD310702PCL
LCSC Part #
C17502885
Packaging
PDIP-16
Customer #
Key Attributes
500mW 180mV 4 P-Channel PDIP-16 FET, MOSFET Arrays RoHS
Datasheetpdf iconAdvanced Linear Devices ALD310702PCL
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QtyUnit Price(Reference Only)Total Amount
1+$ 13.314$ 13.31
200+$ 5.3126$ 1062.52
500+$ 5.1348$ 2567.40
1,000+$ 5.0475$ 5047.50
Standard Packaging50/Full Tube
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Products Specifications

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TypeDescription
CategoryDiscrete Semiconductors/Transistors/FETs, MOSFETs/FET, MOSFET Arrays
ManufacturerAdvanced Linear Devices
PackagingPDIP-16
Configuration-
Current - Continuous Drain(Id)-
RDS(on)-
Pd - Power Dissipation500mW
Gate Threshold Voltage (Vgs(th))180mV
Drain to Source Voltage8V
TypeP-Channel
Reverse Transfer Capacitance (Crss@Vds)-
Number4 P-Channel
Input Capacitance(Ciss)2.5pF
Gate Charge(Qg)-
Operating Temperature0℃~+70℃
Output Capacitance(Coss)-

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging50
Sales UnitPiece

Introduction

AI Translation

The ALD310702A/ALD310702 high-precision monolithic quad P-channel MOSFET array is factory-trimmed using proven EPAD CMOS technology. Available in a quad-channel version, this device is a member of the EPAD matched-pair MOSFET family. The ALD310702A/ALD310702 is the P-channel counterpart to the popular ALD110802A/ALD110802 precision threshold devices. Together, these two MOSFET families enable circuits based on complementary precision N-channel and P-channel MOSFET arrays.

The ALD310702A/ALD310702 is suited for low-voltage and low-power small-signal applications, featuring a precision gate threshold voltage of -0.20V. This allows circuit designs to operate at very low supply voltages — such as < +0.5V — where the circuit operates below the threshold voltage of the ALD310702A/ALD310702. This characteristic also extends the operating range of input/output signals, particularly in ultra-low operating voltage environments. Using these low-threshold precision devices, circuits with multiple cascaded stages can be constructed to operate at extremely low supply or bias voltage levels. The ALD310702A/ALD310702 also features high input impedance (2.5×10¹⁰Ω) and high DC current gain (>10⁸).

The ALD310702A/ALD310702 MOSFETs are designed for excellent matching of device electrical characteristics. The gate threshold voltage VGS(th) is precisely set to -0.20V ± 0.02V, with a typical offset voltage of only ±0.001V (1mV). Since these devices reside on the same monolithic die, they also exhibit excellent thermal tracking characteristics. They serve as general-purpose design building blocks for a wide range of precision analog applications, including current mirrors, matched circuits, current sources, differential amplifier input stages, transmission gates, and multiplexers. These devices also excel in limited supply voltage applications such as ultra-low-level precision voltage clamping. Beyond the matched-pair electrical characteristics, each individual MOSFET features well-controlled manufacturing parameters, enabling users to rely on tight design limits across different production lots.

Designed to provide minimum offset voltage and differential thermal response, these devices are also suitable for switching and amplification applications in -0.40V to -8.0V (±0.20V to ±4.0V) supply systems that require low input bias current, low input capacitance, and fast switching speed. These devices feature well-controlled turn-off and subthreshold characteristics, operating in the same manner as standard enhancement-mode P-channel MOSFETs. However, the precision of the gate threshold voltage introduces two key additional characteristics or operating features. First, at or below the gate threshold voltage (subthreshold region), the operating current level varies exponentially with gate bias voltage. Second, circuits can be biased and operated in the subthreshold region at bias currents in the nA range and power dissipation in the nW range.

For most general-purpose applications, connect the V+ pin to the highest positive voltage in the system, and the V− and IC (internally connected) pins to the lowest negative voltage in the system. The voltages on all other pins must remain within these voltage limits at all times. Standard ESD protection measures and handling procedures for electrostatic-sensitive devices are required when handling these devices.

Features

AI Translation
  • Precision matched gate threshold voltage
  • Precision offset voltage (Vos): ALD310702A: typical 1mV; ALD310702: typical 2mV
  • Subthreshold voltage operation
  • Minimum operating voltage below 0.2V
  • Minimum operating current below 1nA
  • Micro-power operation
  • Wide dynamic operating current range
  • Exponential operating current range
  • Matched transconductance and output conductance
  • Matched and tracking temperature characteristics
  • Tight lot-to-lot parameter control
  • Positive, zero, and negative VGS(th) temperature coefficient bias current
  • Low input capacitance
  • Low input/output leakage current

Applications

AI Translation
  • 0.5% accuracy current mirrors and current sources
  • Low temperature coefficient (<= 50ppm/°C) current mirrors/sources
  • Energy harvesting circuits
  • Ultra-low voltage analog and digital circuits
  • Backup battery circuits and power failure detectors
  • Precision low-level voltage clamps
  • Low-level zero-crossing detectors
  • Source followers and buffers
  • Precision capacitive probe and sensor interfaces
  • Precision charge detectors and charge integrators
  • Discrete differential amplifier input stages
  • Peak detectors and level translators
  • High-side switches and sample-and-hold switches
  • Precision current multipliers
  • Discrete analog switches/multiplexers
  • Discrete voltage comparators