ISSI IS43TR16256B-125KBLI-TR

DDR3 SDRAM power-up and initialization requires the following steps: 1. Power-up (it is recommended to keep RESET# below 0.2×VDD; all other inputs may be undefined). RESET# must be held low for a minimum of 200 microseconds with stable power supply. CKE must be pulled low (minimum 10 nanoseconds) at any time before RESET# is released. The power supply voltage rise time from 300mV to VDD(min) must not exceed 200ms; and during the ramp-up period, VDD > VDDQ and (VDD - VDDQ) < 0.3V. VDD and VDDQ are driven by a single power converter output, and the voltage levels of all pins other than VDD, VDDQ, VSS, and VSSQ must be less than or equal to VDDQ and VDD on one side and greater than or equal to VSSQ and VSS on the other side. In addition, after power-up is complete, VTT is limited to a maximum of 0.95V, and Vref tracks VDDQ/2. Alternatively, VDD may be applied before or simultaneously with VDDQ with no slope reversal; VDDQ may be applied before or simultaneously with VTT and Vref with no slope reversal; the voltage levels of all pins other than VDD, VDDQ, VSS, and VSSQ must be less than or equal to VDDQ and VDD on one side and greater than or equal to VSSQ and VSS on the other side. 2. After RESET# is released, wait an additional 500 microseconds until CKE becomes valid. During this period, the DRAM will begin internal state initialization, which will be completed independently of the external clock. 3. The clock (CK, CK#) must be started and stable for at least 10 nanoseconds or 5 tCK (whichever is greater) before CKE becomes valid. Since CKE is a synchronous signal, the setup time (tIS) relative to the clock must be met. In addition, a NOP or deselect command (with tIS setup time relative to the clock) must be registered before CKE becomes valid. Once CKE is registered high after reset, CKE must remain continuously registered high until the initialization sequence is complete, including the expiration of tDLLK and tZQinit. 4. As long as RESET# is asserted, the DDR3 SDRAM keeps its on-die termination in a high-impedance state. Furthermore, after RESET# is released, the SDRAM keeps its on-die termination in a high-impedance state until CKE is registered high. The ODT input signal may be in an undefined state within tIS time before CKE is registered high.

• Standard Voltage: VDD and VDDo = 1.5V ± 0.075V Low Voltage (L): VDD and VDDo = 1.35V + 0.1V, -0.067V
• Backward compatible to 1.5V
• High speed data transfer rates with system frequency up to 1066 MHz
• 8 internal banks for concurrent operation
• 8n-Bit pre-fetch architecture
• Programmable CAS Latency
• Programmable Additive Latency: 0, CL - 1, CL - 2
• Programmable CAS WRITE latency (CWL) based on tCK
• Programmable Burst Length: 4 and 8
• Programmable Burst Sequence: Sequential or Interleave
• BL switch on the fly
• Auto Self Refresh(ASR)
• Self Refresh Temperature(SRT) Refresh Interval: 7.8 µs (8192 cycles/64 ms) Tc = -40℃ to 85℃; 3.9 µs (8192 cycles/32 ms) Tc = 85℃ to 105℃; 1.95 µs (8192 cycles/16 ms) Tc = 105℃ to 115℃; 0.97 µs (8192 cycles/8 ms) Tc = 115℃ to 125℃
• Partial Array Self Refresh
• Asynchronous RESET pin
• TDQS (Termination Data Strobe) supported (x8 only)
• OCD (Off-Chip Driver Impedance Adjustment)
• Dynamic ODT (On-Die Termination)
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240 Ω)
• Write Leveling Up to 200MHz in DLL off mode
• Operating temperature: Commercial (Tc = 0℃ to +95℃); Industrial (Tc = -40℃ to +95℃); Automotive, A1 (Tc = -40℃ to +95℃); Automotive, A2 (Tc = -40℃ to +105℃); Automotive, A25 (Tc = -40℃ to +115℃); Automotive, A3 (Tc = -40℃ to +125℃)