Infineon SAH-XC2361A72F100LAAHXUMA1

Products Specifications

Type	Description	All
Category	Integrated Circuits (ICs)/Interface/Specialized
Manufacturer	Infineon
Packaging	-
Features	Interrupt generation;Wake-up function;Non-volatile configuration storage

AI Translation

High-performance CPU with five-stage pipeline and MPU
12.5 ns instruction cycle at 80 MHz CPU clock (single-cycle execution)
One-cycle 32-bit addition and subtraction with 40-bit result
One-cycle multiplication (16×16 bit)
Background division (32 / 16 bit) in 21 cycles
One-cycle multiply-and-accumulate (MAC) instructions
Enhanced Boolean bit manipulation facilities
Zero-cycle jump execution
Additional instructions to support HLL and operating systems
Register-based design with multiple variable register banks
Fast context switching support with two additional local register banks
16 Mbytes total linear address space for code and data
1024 Bytes on-chip special function register area (C166 Family compatible)
Integrated Memory Protection Unit (MPU)
Interrupt system with 16 priority levels for up to 96 sources
Selectable external inputs for interrupt generation and wake-up
Fastest sample-rate 12.5 ns
Eight-channel interrupt-driven single-cycle data transfer with Peripheral Event Controller (PEC), 24-bit pointers cover total address space
Clock generation from internal or external clock sources, using on-chip PLL or prescaler
Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip Memory Areas
On-chip memory modules
8 Kbytes on-chip stand-by RAM (SBRAM)
2 Kbytes on-chip dual-port RAM (DPRAM)

Not available now