NXP LPC11U68JBD48E

The LPC11U3x are an ARM Cortex - M0 based, low - cost 32 - bit MCU family, designed for 8/16 - bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16 - bit architectures. The LPC11U3x operate at CPU frequencies of up to 50 MHz. Equipped with a highly flexible and configurable full - speed USB 2.0 device controller, the LPC11U3x brings unparalleled design flexibility and seamless integration to today’s demanding connectivity solutions. The peripheral complement of the LPC11U3x includes up to 128 kB of flash memory, up to 12 kB of SRAM data memory and 4 kB EEPROM, one Fast - mode Plus I2C - bus interface, one RS - 485/EIA - 485 USART with support for synchronous mode and smart card interface, two SSP interfaces, four general purpose counter/timers, a 10 - bit ADC, and up to 54 general purpose I/O pins. The I/O Handler is a software library - supported hardware engine that can be used to add performance, connectivity and flexibility to system designs. It is available on the LPC11U37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART, I2C, and I2S with no or very low additional CPU load and can off - load the CPU by performing processing - intensive functions like DMA transfers in hardware. Software libraries for multiple I/O Handler applications are available on nxp.com.

• ARM Cortex - M0 processor, running at frequencies of up to 50 MHz.
• ARM Cortex - M0 built - in Nested Vectored Interrupt Controller (NVIC).
• Non - Maskable Interrupt (NMI) input selectable from several input sources.
• System tick timer.
• Up to 128 kB on - chip flash program memory with sector (4 kB) and page erase (256 byte) access.
• 4 kB on - chip EEPROM data memory; byte erasable and byte programmable; on - chip API support.
• Up to 12 kB SRAM data memory.
• 16 kB boot ROM.
• In - System Programming (ISP) and In - Application Programming (IAP) via on - chip bootloader software.
• ROM - based USB drivers. Flash updates via USB supported.
• ROM - based 32 - bit integer division routines.
• Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan Description Language).
• Serial Wire Debug.
• Up to 54 General Purpose I/O (GPIO) pins with configurable pull - up/pull - down resistors, repeater mode, and open - drain mode.
• Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
• Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
• High - current source output driver (20 mA) on one pin.
• High - current sink driver (20 mA) on true open - drain pins.
• Four general purpose counter/timers with a total of up to 8 capture inputs and 13 match outputs.
• Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal low - power WatchDog Oscillator (WDO).
• 10 - bit ADC with input multiplexing among eight pins.
• USB 2.0 full - speed device controller.
• USART with fractional baud rate generation, internal FIFO, a full modem control handshake interface, and support for RS - 485/9 - bit mode and synchronous mode. USART supports an asynchronous smart card interface (ISO 7816 - 3).
• Two SSP controllers with FIFO and multi - protocol capabilities.
• I2C - bus interface supporting the full I2C - bus specification and Fast - mode Plus with a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
• I/O Handler for hardware emulation of serial interfaces and DMA; supported through software libraries. (LPC11U37HFBD64/401 only.)
• Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
• 12 MHz high - frequency Internal RC oscillator (IRC) that can optionally be used as a system clock.
• Internal low - power, low - frequency WatchDog Oscillator (WDO) with programmable frequency output.
• PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources.
• A second, dedicated PLL is provided for USB.
• Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator.
• Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep - sleep, Power - down, and Deep power - down modes.
• Power profiles residing in boot ROM provide optimized performance and minimized power consumption for any given application through one simple function call.
• Four reduced power modes: Sleep, Deep - sleep, Power - down, and Deep power - down.
• Processor wake - up from Deep - sleep and Power - down modes via reset, selectable GPIO pins, watchdog interrupt, or USB port activity.
• Processor wake - up from Deep power - down mode using one special function pin.
• Power - On Reset (POR).
• Brownout detect with up to four separate thresholds for interrupt and forced reset.
• Unique device serial number for identification.
• Single 3.3 V power supply (1.8 V to 3.6 V).
• Temperature range - 40 ℃ to + 85 ℃.
• Available as LQFP64, LQFP48, TFBGA48, and HVQFN33 packages.