TI TMS320C6454BGTZA

The TMS320C64x+ DSPs (including the TMS320C6454 device) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The C6454 device is based on the third-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture, making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible from previous devices that are part of the C6000 DSP platform. The C6454 device offers a lower cost pin-compatible migration path for C6455 customers who don't need the 2MB of the C6455 or the high-speed interconnect provided by Serial RapidIO. The C6454 device also provides an excellent migration path for existing C6414/6415/6416 customers who require C6454 advanced peripherals; DDR2 at 533 MHz provides 2x performance boost over older SDRAM interface, gigabit Ethernet provides low-cost high-performance ubiquitous packet interface, and 66-MHz PCI (revision 2.3 complaint) provides legacy high-bandwidth interconnect. Based on 90-nm process technology and with performance of up to 8000 million instructions per second (MIPS) [or 8000 16-bit MMACs per cycle] at a 1-GHz clock rate, the C6454 device offers cost-effective solutions to high-performance DSP programming challenges. The C6454 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The G64x+ DSP core employs eight functional units, two register files, and two data paths. Two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the G64x+ core. At a 1-GHz clock rate, this means 8000 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle. The C6454 DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on the C6454 device are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The level-2 (L2) memory is shared between program and data space and is 1048KB in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. The G64x+ Megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp. The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial ports (McBSPs); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral c

• High-Performance Fixed-Point DSP (C6454)
  • 1.39-, 1.17-, and 1-ns Instruction Cycle Time
  • 720-MHz, 850-MHz, and 1-GHz Clock Rate
  • Eight 32-Bit Instructions/Cycle
  • 8000 MIPS/MMACS (16-Bits)
  • Commercial Temperature [0℃ to 90℃]
  • Extended Temperature [-40℃ to 105℃]
• TMS320C64x+ DSP Core
  • Dedicated SPLOOP Instruction
  • Compact Instructions (16-Bit)
  • Instruction Set Enhancements
  • Exception Handling
• TMS320C64x+ Megamodule L1/L2 Memory Architecture:
  • 256K-Bit (32K-Byte) L1P Program Cache [Direct Mapped]
  • 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-Associative]
  • 8M-Bit (1048K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • 256K-Bit (32K-Byte) L2 ROM
  • Time Stamp Counter
• Endianess: Little Endian, Big Endian
• 64-Bit External Memory Interface (EMIFA)
  • Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM)
  • Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
  • 32M-Byte Total Addressable External Memory Space
• DDR2 Memory Controller
  • Interfaces to DDR2-533 SDRAM
  • 32-Bit/16-Bit, 533-MHz (data rate) Bus
  • 512M-Byte Total Addressable External Memory Space
• EDMA3 Controller (64 Independent Channels)
• 32-/16-Bit Host-Port Interface (HPI)
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification (v2.3)
• One Inter-Integrated Circuit (I²C) Bus
• Two McBSPs
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
  • IEEE 802.3 Compliant
  • Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII)
  • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
• Two 64-Bit General-Purpose Timers, Configurable as Four 32-Bit Timers
• 16 General-Purpose I/O (GPIO) Pins
• System PLL and PLL Controller
• Secondary PLL and PLL Controller, Dedicated to EMAC and DDR2 Memory Controller
• Advanced Event Triggering (AET) Compatible
• Trace-Enabled Device
• IEEE-1149.1 (JTAG) Boundary-Scan Compatible
• 697-Pin Ball Grid Array (BGA) Package (CTZ, GTZ, or ZTZ Suffix), 0.8-mm Ball Pitch
• 0.09-μm/7 -Level Cu Metal Process (CMOS)
• 3.3-/1.8-/1.5-V I/Os, 1.25-/1.2-V Internal
• Pin-Compatible with the TMS320C6455 FixedPoint Digital Signal Processor

• Video and telecom infrastructure
• Imaging/medical
• Wireless infrastructure (WI)