NXP MCIMX6Z0DVM09AB

The i.MX 6ULZ processor is the ultra low cost extension of the i.MX 6ULL family product, which offering high performance processing with a high degree of functional integration and targeted towards the growing market of connected devices. The i.MX 6ULZ is a high performance, ultra efficient processor family with featuring NXP’s advanced implementation of the single Arm Cortex -A7 core, which operates at speeds of up to 900 MHz. i.MX 6ULZ includes integrated power management module that reduces the complexity of external power supply and simplifies the power sequencing. Each processor in this family provides various memory interfaces, including LPDDR2, DDR3, DDR3L, Raw and Managed NAND flash, NOR flash, eMMC, Quad SPI, a wide range of other interfaces for audio processing, and connecting peripherals, such as WLAN, Bluetooth, and GPS.

• Single-core Arm Cortex-A7: The single core A7 provides a cost-effective and power-efficient solution.
• Multilevel memory system: The multilevel memory system of processor is based on the L1 instruction and data caches, L2 cache, and internal and external memory. The processor supports many types of external memory devices, including DDR3, low voltage DDR3, LPDDR2, NOR Flash, NAND Flash (MLC and SLC), OneNAND, Quad SPI, and managed NAND, including eMMC up to rev 4.4/4.41/4.5.
• Smart speed technology: Power management implemented throughout the IC that enables multimedia features and peripherals to consume minimum power in both active and various low power modes.
• Dynamic voltage and frequency scaling: The power efficiency of devices by scaling the voltage and frequency to optimize performance.
• Interface flexibility: Each processor supports connections to a variety of interfaces: two high-speed USB on-the-go with PHY, multiple expansion card ports (high-speed MMC/SDIO host and other).
• Integrated power management: The processors integrate linear regulators and internally generate voltage levels for different domains. This significantly simplifies system power management structure.
• Supports single Arm Cortex-A7 MPCore (with TrustZone) with:
  • 32 KB L1 Instruction Cache
  • 32 KB L1 Data Cache
  • Private Timer and Watchdog
  • Cortex-A7 NEON Media Processing Engine (MPE) Co-processor
  • General Interrupt Controller (GIC) with 128 interrupts support
  • Global Timer
  • Snoop Control Unit (SCU)
  • 128 KB unified I/D L2 cache
  • Single Master AXI bus interface output of L2 cache
  • Frequency of the core (including Neon and L1 cache), as per Table 9, "Operating ranges," on page 19.
  • NEON MPE coprocessor
    • SIMD Media Processing Architecture
    • NEON register file with 32x64-bit general-purpose registers
    • NEON Integer execute pipeline (ALU, Shift, MAC)
    • NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
    • NEON load/store and permute pipeline
    • 32 double-precision VFPv3 floating point registers
• The SoC-level memory system consists of the following additional components:
  • Boot ROM, including HAB (96 KB)
  • Internal multimedia/shared, fast access RAM (OCRAM, 128 KB)
• External memory interfaces: The i.MX 6ULZ processors support latest, high volume, cost effective handheld DRAM, NOR, and NAND Flash memory standards.
  • 16-bit LP-DDR2-80

• Telematics
• Audio playback
• Connected devices
• IoT Gateway
• Access control panels
• Portable medical and health care
• Smart appliances