TI SN74ALS112AN

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE (overline)) or clear (CLR (overline)) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE (overline) and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.