RENESAS 82V3910AUG

The 82V3910 Synchronous Ethernet (SyncE) SETS meets the requirements of ITU-T G.8262/G.813 for EEC/SEC options 1 and 2; and it meets the requirements of Telcordia GR-253-CORE Stratum 3 (S3) and SONET Minimum Clock (SMC). The 82V3910 ultra-low jitter output clocks can be used to directly synchronize 10GBASE-R/10GBASE-W and OC-192/STM-64 PHYs and 40GBASE-R PHYs in Synchronous Ethernet and SONET/SDH equipment. The Synchronous Equipment Timing Source (SETS) functions are provided by two independent digital PLLs (DPLLs), T0 and T4, each with embedded clock synthesizers. The T0 DPLL meets the network synchronization requirements for frequency accuracy, pull-in, hold-in, pullout, noise generation, noise tolerance, transient response and holdover performance. The T4 DPLL provides rate conversion functions that can be used, for example, to convert a recovered line clock to a 1.544 MHz, 2.048MHz or 64 kHz synchronization reference for external equipment. The 82V3910 provides ten single ended reference inputs and two differential reference inputs that can operate at common Ethernet, SONET/ SDH and PDH frequencies and other frequencies. The device also provides two Alternate Mark Inversion (AMI) inputs for Composite Clock (CC) signals bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The references are continually monitored for loss of signal and for frequency offset per user programmed thresholds. All of the references are available to both digital PLLs (DPLLs). The active reference for each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allowances and based on the reference monitors. The 82V3910 can accept a clock reference and a phase locked external sync signal as a pair. The T0 DPLL can lock to the reference clock input and align its frame sync and multi-frame sync outputs with the paired external sync input. The device provides to two external sync inputs that can be associated with any of the twelve reference inputs to create up to two pairs. The external sync signals can have a frequency of 1 Hz, 2 kHz or 8 kHz.

• Jitter generation < 0.3 ps RMS (10 kHz to 20 MHz), meets jitter generation requirements of leading PHYs supporting 10GBASE-R, 10GBASE-W, 40GBASE-R, OC-192 and STM-64
• Features 0.5 mHz to 35 Hz bandwidth
• Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE)
• Provides node clocks for Cellular and WLL base-station (GSM and 3G networks)
• Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments
• Provides clocks for 1 Gigabit, 10 Gigabit, and 40 Gigabit Ethernet
• Supports clock generation for IEEE-1588 applications
• Provides an integrated solution for Synchronous Equipment Timing Source, including Stratum 3, SMC, EEC-Option 1 and EEC Option 2 Clocks
• Integrates T4 DPLL and T0 DPLL; T4 DPLL locks independently or locks to T0 DPLL
• Supports programmable DPLL bandwidth (0.5 mHz to 35 Hz) and damping factor (1.2 to 20 in 5 steps)
• Supports 1.1×10⁻⁵ ppm absolute holdover accuracy and 4.4×10⁻⁸ ppm instantaneous holdover accuracy
• Supports hitless reference switching to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
• Integrates 2 jitter attenuating APLLs to generate ultra-low jitter clocks
• Supports 3 clock modes: SONET, Ethernet, and Ethernet LANPHY
• Supports up to two crystal connections, allowing each APLL to support up to two modes of operation
• Supports input and output clocks whose frequencies range from 1PPS to 644.53125 MHz
• Includes 1PPS clock input and output
• Provides IN1 and IN2 for 64kHz + 8 kHz or 64kHz + 8kHz + 0.4kHz composite clocks
• Provides IN3, IN4, IN7~IN14 input CMOS clocks whose frequencies range from 1PPS to 156.25 MHz
• Provides IN5 and IN6 input differential clocks whose frequencies range from 1PPS to 625 MHz
• Provides OUT1 to OUT5 output CMOS clocks whose frequency cover from 1PPS to 125 MHz
• Provides OUT6, OUT7, OUT10 and OUT11 output differential clocks whose frequency cover from 25 MHz to 644.53125 MHz
• Provides OUT8 for composite clocks and OUT9 for 1.544 MHz/ 2.048 MHz (BITS/SSU)
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Provides a 1PPS, 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and a 1PPS, 2 kHz or 8 kHz frame sync output signal
• Internal DCO can be controlled by an external processor to be used for IEEE-1588 clock generation
• Supports programmable input-to-output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Supports Forced or Automatic operating mode switch controlled by an internal state machine. Automatic mode switch supports FreeRun, Locked and Holdover modes
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock failure
• Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing
• Supports AMI, LVPECL/LVDS and CMOS input/output technologies
• Supports Master/Slave application (two chips used together) to enable system protection against single chip failure
• Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recommendations
• I2C Microprocessor interface
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 1mm ball pitch CABGA green package

• SMC / SEC (SONET / SDH equipment)
• EEC (Synchronous Ethernet equipment)
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipment