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TI SN74LV4046ADR
| Manufacturer | |
| MPN | SN74LV4046ADR |
| LCSC Part # | C1535635 |
| Packaging | SOIC-16 |
| Customer # | |
| Key Attributes | 38MHz 3V~5.5V 3 SOIC-16 Clock Generators, PLLs, Frequency Synthesizers RoHS |
| Datasheet |  TI SN74LV4046ADR |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Operating Temperature | -40℃~+125℃ | |
| Clock/Oscillator | External | |
| Output Frequency(Max) | 38MHz | |
| Voltage - Supply | 3V~5.5V | |
| Period Jitter, Peak-to-Peak | -;- | |
| Phase Offset | Not supported | |
| Features | On-chip VCO/DCO;Built-in phase-locked loop | |
| Output Level | CMOS;TTL | |
| Phase Jitter | - | |
| Number of Outputs | 3 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7. The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator. The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive lowpass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. Various applications include telecommunications, digital phase-locked loop and signal generators.
Features
- ESD Protection Exceeds JESD 22 2000-V Human Body Model (A114-A) 1000-V Charged-Device Model (C101)
- Choice of Three Phase Comparators
- Exclusive OR Edge-Triggered J-K Flip-Flop
- Edge-Triggered RS Flip-Flop
- Excellent VCO Frequency Linearity
- VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
- Optimized Power-Supply Voltage Range From 3 V to 5.5 V
- Wide Operating Temperature Range From -40°C to +125°C
- Latch-Up Performance Exceeds 250 mA Per JESD 17
Applications
- Telecommunications
- Signal Generators
- Digital Phase-Locked Loop
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 1.5592 | $ 1.56 |
| 10+ | $ 1.3737 | $ 13.74 |
| 30+ | $ 1.2435 | $ 37.31 |
| 100+ | $ 1.123 | $ 112.30 |
| 500+ | $ 1.0677 | $ 533.85 |
| 1,000+ | $ 1.0449 | $ 1044.90 |
Standard Packaging2500/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers | |
| Manufacturer | TI | |
| Packaging | SOIC-16 | |
| Operating Temperature | -40℃~+125℃ | |
| Clock/Oscillator | External | |
| Output Frequency(Max) | 38MHz | |
| Voltage - Supply | 3V~5.5V | |
| Period Jitter, Peak-to-Peak | -;- | |
| Phase Offset | Not supported | |
| Features | On-chip VCO/DCO;Built-in phase-locked loop | |
| Output Level | CMOS;TTL | |
| Phase Jitter | - | |
| Number of Outputs | 3 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 2500 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7. The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator. The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive lowpass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. Various applications include telecommunications, digital phase-locked loop and signal generators.
Features
- ESD Protection Exceeds JESD 22 2000-V Human Body Model (A114-A) 1000-V Charged-Device Model (C101)
- Choice of Three Phase Comparators
- Exclusive OR Edge-Triggered J-K Flip-Flop
- Edge-Triggered RS Flip-Flop
- Excellent VCO Frequency Linearity
- VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
- Optimized Power-Supply Voltage Range From 3 V to 5.5 V
- Wide Operating Temperature Range From -40°C to +125°C
- Latch-Up Performance Exceeds 250 mA Per JESD 17
Applications
- Telecommunications
- Signal Generators
- Digital Phase-Locked Loop
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |