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RENESAS 8V19N492NLGI product image
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RENESAS 8V19N492NLGIRoHS

Manufacturer
MPN
8V19N492NLGI
LCSC Part #
C1535606
Packaging
VFQFPN-88(10x10)
Customer #
Key Attributes
2.949GHz 1 VFQFPN-88(10x10) Clock Generators, PLLs, Frequency Synthesizers RoHS
Datasheetpdf iconRENESAS 8V19N492NLGI
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QtyUnit Price(Reference Only)Total Amount
1+$ 29.8465$ 29.85
30+$ 28.3036$ 849.11
Standard Packaging168/Full Tray
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers
ManufacturerRENESAS
PackagingVFQFPN-88(10x10)
Operating Temperature-
Voltage - Supply-
Output Frequency(Max)2.949GHz
FeaturesProgrammable phase and delay control;Output synchronization;Fail-hold;Automatic clock switching
Output LevelLVPECL;LVDS
Number of Outputs1

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging168
Sales UnitPiece

Introduction

AI Translation

The 8V19N49x FemtoClock NG family of RF sampling clock generators with jitter attenuation supports 5G New Radio (NR) designs for wireless base station radio equipment boards. The devices are optimized to deliver excellent phase noise and spurious performance for radio board implementations. The 8V19N49x family provides very-low phase skew drift in temperature, reducing radio path recalibration occurrences in beamforming applications. These devices generate up to five clock frequencies from an internal VCO(s) distributed to up to 18 low-skew differential outputs. An integrated pulse generator provides JESD204B-compliant SYSREF synchronization signals. The outputs support symmetrical 100Ω (LVDS type) and LVPECL 50Ω termination, with a configurable amplitude up to 2000mV differential. Integrated phase delay circuits enable clock / SYSREF phase adjustments to meet stringent receiver hold / setup time requirements, achieving zero device delay and board trace length compensation.

Features

AI Translation
  • Supports RF DAC sampling clocks
    • 2.94912GHz
    • 2.4576GHz
    • 1.96608GHz
    • 3.6864GHz
    • 3.93216GHz
  • Optimized for low Error Vector Magnitude (EVM) radio designs
  • Single chip solution for 4T4T to 16T16R
  • Ideal for synchronous clock / SYSREF generation in AAS and MIMO
  • JESD204B subclass 0 / 1 converter synchronization
  • High fanout options reduce clock buffer component count
  • Cascaded operation and very-low output skew temperature drift for MIMO and beamforming applications
  • Deterministic phase relationship and alignment

Applications

AI Translation
  • Wireless infrastructure radio
  • Reference clock for high-speed, high-performance DAC / ADC
  • JESD204B synchronization
  • Instrumentation
  • CPRI