SILICON LABS SI4010-C200FGT

The Si4010 is a fully integrated crystal-less CMOS SoC RF transmitter with an embedded CIP-51 8051 MCU. The device can operate over the -40 to 85 °C temperature range without requiring an external crystal reference source reducing board area and BOM cost. The device includes an 8 kB non volatile memory block for programming the user's application along with a 12 kB ROM of embedded support code for use in the user's application. The Si4010 includes 2-wire C2 Debug and Programming interface, which allows customers to download their code during the development stage into the on-board RAM for testing and debug prior to programming the NVM.

Garage and gate door openers Remote keyless entry Home automation and security Wireless remote controls

The Si4010 is designed for low power battery applications with standby currents of less than 10 nA to optimize battery life and features automatic wake on button press support to efficiently move from the standby to active mode state with minimal customer code support. Built in AES-128 hardware encryption along with a 128-bit EEPROM can be used to create robust data encryption of the transmitted packets. A unique 4-byte serial number is programmed into each device ensuring non-overlapping device identifiers.

The RF transmitter features a high efficiency PA capable of delivering output power up to +10 dBm and includes an automatic antenna tuning algorithm. This algorithm adjusts the antenna tuning at the start of each packet transmission for optimal output power minimizing the impact of antenna impedance changes due to the remote being held in a user hand. The devices supports FSK and OOK modulations and includes automatic output power shaping to reduce spectral spreading and ease regulatory compliance. The output frequency can be adjusted via software over the entire 27 to 960MHz range. The output data rate is software adjustable up to a maximum rate of 100kbps.

• Crystal-less operation
• Optional crystal oscillator input
• High-Speed 8051 μC Core
• Pipeline instruction architecture
• 70% of instructions in 1 or 2 clocks
• Up to 24 MIPs with 24 MHz clock
• 4 kB RAM/8kB NVM
• 128 bit EEPROM
• 256 byte of internal data RAM
• 12 kB ROM embedded functions
• 8 byte low leakage RAM
• Extensive Digital Peripherals
• 128 bit AES accelerator
• 5/9 GPIO with wakeup functionality
• LED driver
• Data serializer
• High-speed frequency counter
• On-chip debugging: C2
• Unique 4 byte serial number
• Ultra low-power sleep timer

• Single Coin-Cell Battery Operation
• High-performance RF transmitter
• Analog Peripherals