Broadcom PEX8619-BA50BI G

The ExpressLane PEX 8619 device provides PCI Express switching functionality, enabling users to add scalable, high-bandwidth, non-blocking interconnects across a variety of applications, including control plane, communications platforms, servers, storage systems, and embedded systems. The device is well-suited for fan-out, aggregation, point-to-point, and intelligent I/O module applications. Its architecture supports packet cut-through with a maximum latency of 140ns, combined with large-capacity packet memory and a non-blocking internal switch fabric to deliver full line-rate performance on all ports, making it ideal for low-latency applications such as communications and servers. Low latency contributes to high throughput and performance. The device also supports a maximum payload size of 2048 bytes for higher throughput. It integrates a versatile and powerful DMA engine that can operate as a standalone engine, offloading the processor from the burden of device-to-device data transfers so it can focus on computational tasks. Four DMA channels support high-speed data transfers between I/O devices connected to any available port on the PEX 8619. The DMA engine can also complement the processor's DMA engine by providing additional channels for higher performance. The device offers end-to-end CRC protection and poison bit support for designs requiring guaranteed error-free packet delivery. It also supports data path parity and memory error correction. The PEX 8619 supports full non-transparent bridging functionality for multi-host systems and intelligent I/O modules, targeting communications, storage, and server applications requiring redundancy support. The non-transparent bridge allows a system to isolate host memory domains by presenting a processor subsystem as an endpoint rather than another memory system. It uses Base Address Registers for address translation, doorbell registers for sending interrupts between address domains, and scratchpad registers accessible from both address domains for inter-processor communication. The device is fully compliant with the PCI Express Base Specification Revision 2.0 and is backward compatible with Revisions 1.1 and 1.0a. Each port supports auto-negotiation, lane reversal, and polarity inversion. Additionally, the device is designed to meet Microsoft Vista requirements. All ports support hot-plug capability via an I²C interface for high-availability applications. If a downstream port is connected to a PCI Express slot, the hot-plug controller for each port can be used to manage hot-plug events for its associated slot. Each port is equipped with hot-plug control/status registers. The device supports multicast functionality, allowing data to be replicated from one ingress port to two egress ports, enabling higher performance in applications such as storage and security.

• 16-lane PCI Express switch
• Integrated 5.0 GT/s SerDes
• Up to 16 configurable ports
• 19×19mm², 324-ball HSBGA package
• Typical power consumption: 1.99W
• Compliant with PCI Express Base Specification Revision 2.0 (backward compatible with PCIe 1.0a/1.1)
• Compliant with PCI Power Management Specification 1.2
• Meets Microsoft Vista requirements
• Access Control Services support
• Dynamic link width control
• Integrated DMA engine
• Four DMA channels
• Internal descriptor support
• DMA function independent of transparent switching function
• 64-bit addressing
• Prefetch descriptor mode
• Per-channel throughput up to 4.0 GB/s
• Cut-through latency: 140ns
• 2KB maximum payload size
• Read metering
• Multicast
• Configurable non-transparent ports
• Movable upstream port
• Cross-link port capability
• 16 flexibly configurable ports (x1, x4, or x8)
• Configurable via configuration pins, EEPROM, I²C, or host software
• Lane and polarity inversion
• Link power management states: L0, L0s, L1, L2/L3 Ready, and L3
• Device states: D0 and D3 hot
• Spread spectrum clock isolation, dual clock domains
• Two virtual channels per port
• Eight traffic classes per port
• Weighted round-robin port and virtual channel arbitration
• Hot-plug via I²C supported on all ports (hot-plug controller per port)
• Data path protection
• Memory error correction
• Port status bits and GPIO available
• Per-port error diagnostics
• Performance monitoring (per-port payload and header counters)

• Control Plane
• Communications Platform
• Server
• Storage System
• Embedded System