TI OMAPL138EZWTA3E

The OMAP-L138 C6000 DSP + ARM processor is a low-power application processor based on the ARM926EJ-S and C674x DSP cores. Compared with other TMS320C6000 platform DSPs, it consumes significantly less power. This device features a dual-core architecture (including a high-performance TMS320C674x DSP core and an ARM926EJ-S core), which perfectly combines the advantages of DSP and Reduced Instruction Set Computer (RISC) technologies.

The ARM926EJ-S is a 32-bit RISC processor core that can execute 32-bit or 16-bit instructions and process 32-bit, 16-bit, or 8-bit data. The core uses a pipelined structure, allowing all components of the processor and memory system to operate continuously. The ARM9 core is equipped with Coprocessor 15 (CP15), a protection module, and a data and program Memory Management Unit (MMU) with a page table buffer. It also has separate 16KB instruction cache and 16KB data cache, both of which are 4-way set associative with Virtual Index Virtual Tag (VIVT). The ARM9 core also includes 8KB of RAM (vector table) and 64KB of ROM.

The DSP core of this device uses a two-level cache-based architecture. The Level 1 Program Cache (L1P) is a 32KB direct-mapped cache, and the Level 1 Data Cache (L1D) is a 32KB 2-way set associative cache. The Level 2 Program Cache (L2P) contains 256KB of storage space, shared by the program and data spaces. The L2 memory can be configured as mapped memory, cache, or a combination of both. Although both the ARM9 and other hosts in the system can access the DSP L2, an additional 128KB of shared RAM is provided for other hosts to avoid affecting DSP performance.

For devices supporting security features, TI's Basic Secure Boot protects users' intellectual property and prevents external entities from modifying user-developed algorithms. The secure boot process starts from a hardware-based "root of trust" to ensure that code execution begins from a known secure location. By default, the JTAG port is locked to prevent emulation and debugging attacks; however, it can be enabled during the secure boot process for application development. The boot module is encrypted when stored in external non-volatile memory (e.g., flash or EEPROM) and is decrypted and verified when loaded during secure boot. Encryption and decryption procedures protect user IP, enabling users to securely set up the system and start the device with known trusted code. Basic Secure Boot uses SHA-1 or SHA-256 and AES-128 to verify the boot image. Additionally, it uses AES-128 for boot image encryption. The secure boot process employs a multi-layer encryption mechanism to protect the boot process and securely upgrade boot and application software code.

The device uses a 128-bit device-specific key to protect the user key. This 128-bit key is generated by a random number generator certified by NIST-800-22 and is only known to the device. When an update is required, customers can use the key to create a new encrypted image. The device can then obtain the image via an external interface (e.g., Ethernet) to overwrite the existing code.

The peripheral set includes: a 10Mbps/100Mbps Ethernet Media Access Controller (EMAC) with a Management Data Input/Output Module (MDIO); a USB2.0 OTG interface; a USB1.1 OHCI interface; two I2C bus interfaces; a Multi-Channel Audio Serial Port (McASP) with 16 serializers and FIFO buffers; two Multi-Channel Buffered Serial Ports (McBSP) with FIFO buffers; two Serial Peripheral Interfaces (SPI) supporting multiple chip selects; a configurable 16-bit Host Port Interface (HPI); up to nine groups of General-Purpose Input/Output (GPIO) pins (each group containing 16 pins, each supporting programmable interrupt and event generation modes and multiplexing with other peripherals); three UART interfaces (all supporting RTS and CTS); two Enhanced High-Resolution Pulse Width Modulator (eHRPWM) peripherals; three 32-bit Enhanced Capture (eCAP) module peripherals (configurable as three capture inputs or three APWM outputs); two external memory interfaces (one is an asynchronous SDRAM External Memory Interface (EMIFA) for slow memory or peripherals, and the other is a high-speed DDR2/mobile DDR controller).

The EMAC provides an efficient interface between the device and the network. It supports 10Base-T and 100Base-TX or 10Mbps and 100Mbps in both half-duplex and full-duplex modes. Additionally, the device provides an MDIO interface for PHY configuration. The EMAC supports MII and RMII interfaces.

The Serial ATA (SATA) controller provides a high-speed interface to mass data storage devices. It supports SATA I (1.5Gbps) and SATA II (3.0Gbps).

The Universal Parallel Port (uPP) provides a high-speed interface to various types of data converters, FPGAs, or other parallel devices. Both channels of the uPP support programmable data widths ranging from 8 bits to 16 bits. It also supports single or double data rate transmission and START, ENABLE, and WAIT signals to control various data converters.

The Video Port Interface (VPIF) provides flexible video I/O ports. The rich peripheral set enables control of peripherals and communication with external processors.

The device comes with a complete set of ARM9 and DSP development tools. This set includes a C compiler, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for viewing source code execution.

• Professional/Private Mobile Radio (PMR)
• Remote Radio Unit (RRU) / Remote Radio Head (RRH)
• Industrial Automation
• Banknote Verification
• Biometric Recognition
• Machine Vision (Low-end)
• Smart Grid
• Substation Protection
• Industrial Portable Navigation Devices