NXP MCIMX6V7DVN10AB

The i.MX 6SLL processor represents NXP’s latest achievement in integrated multimedia applications processors, which are part of a growing family of multimedia-focused products that offer high performance processing and are optimized for lowest power consumption. The processor features NXP’s advanced implementation of a single Arm Cortex-A9, which operates at speeds up to 800 MHz. The processor provides a 32-bit DDR interface that supports LPDDR2 and LPDDR3. In addition, there are a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, hard drive, displays, and camera sensors. The i.MX 6SLL processor features: Applications processor—The i.MX 6SLL incorporates a 1 GHz Cortex A9 with the NEON SIMD engine and a floating point engine that is optimized for low power consumption and includes hardware that allows dynamic voltage and frequency scaling (DVFS). This optimizes the voltage to the processor as the frequency changes with the demands of the application. Multilevel memory system—The multilevel memory system for the processor is based on the L1 instruction and data caches, L2 cache, and internal and external memory. The processor supports many types of external memory devices, including LPDDR2, LPDDR3, and eMMC. Powerful graphics acceleration—The processor has a 2D graphics processor called the pixel processor (PXP) that can support CSC, dithering, rotation, resize, and overlay. Interface flexibility—The processor supports connections to a variety of interfaces: high-speed USB on-the-go with PHY, high-speed USB host PHY, multiple expansion card ports (high-speed MMC/SDIO host and other), and a variety of other popular interfaces (such as UART, I²C, and I²S). Electronic Paper Display Controller—The processor integrates EPD controller that supports E-INK color and monochrome with up to 2332 x 1650 resolution and 5-bit grayscale. Advanced security—The processor delivers hardware-enabled security features that enable secure information encryption, secure boot, and secure software downloads. GPIO with interrupt capabilities—The GPIO pad design supports configurable dual voltage rails at 1.8 V and 3.3 V supplies. The pad is configurable to interface at either voltage level.

• Arm Cortex-A9 MPCore CPU processor (with TrustZone)
• The core configuration is symmetric, where each core includes:
  • 32 KByte L1 Instruction Cache 32 KByte L1 Data Cache
  • Private Timer and Watchdog
• Cortex-A9 NEON MPE (Media Processing Engine) co-processor
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• 256 KB unified I/D L2 cache
• Two Master AXI (64-bit) bus interfaces output of L2 cache
• NEON MPE coprocessor — SIMD Media Processing Architecture
• NEON register file with 32x64-bit general-purpose registers
• NEON Integer execute pipeline (ALU, Shift, MAC)
• NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
• NEON load/store and permute pipeline
• Boot ROM, including HAB (96 KB)
• Internal multimedia / shared, fast access RAM (OCRAM, 128 KB)
• 32-bit LPDDR2/LPDDR3

• Color and monochrome eReaders
• Barcode scanners
• Connectivity
• IoT devices